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[209.85.219.52]) by smtp.gmail.com with ESMTPSA id t11-20020a05620a450b00b006eea4b5abcesm12721091qkp.89.2022.12.15.09.26.35 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Dec 2022 09:26:35 -0800 (PST) Received: by mail-qv1-f52.google.com with SMTP id d2so2245145qvp.12 for ; Thu, 15 Dec 2022 09:26:35 -0800 (PST) X-Received: by 2002:a0c:c690:0:b0:4f0:656b:c275 with SMTP id d16-20020a0cc690000000b004f0656bc275mr370160qvj.129.1671125195150; Thu, 15 Dec 2022 09:26:35 -0800 (PST) MIME-Version: 1.0 References: <20221213174234.688534-1-dave.hansen@linux.intel.com> <20221215123007.cagd7qiidehqd77k@box.shutemov.name> In-Reply-To: From: Linus Torvalds Date: Thu, 15 Dec 2022 09:26:19 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [GIT PULL] x86/mm for 6.2 To: kirill.shutemov@linux.intel.com Cc: Dave Hansen , linux-kernel@vger.kernel.org, x86@kernel.org, jejb@linux.ibm.com, martin.petersen@oracle.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Dec 15, 2022 at 9:17 AM Linus Torvalds wrote: > > Here's *one* suggested solution: Note again: this is not a "you need to do it this way" suggestion. This is just a "at least this way doesn't have the issues I object to". There are bound to be other ways to do it. But if you feel like all threads have to share the same LAM state, it does seem a lot simpler if you just say "you need to set that state before you start any threads". No? > And yes, I would actually suggest that _any_ thread creation locks it, > so that you never *EVER* have any issues with "oh, now I need to > synchronize with other threads". A process can set its LAM state at > startup, not in the middle of running! Note that this "no serialization needed" is just about the SW side. The *hardware* side may still need the IPI just to make sure that it forces a TLB flush - even if we are single-threaded, that single thread may have run on other CPU's before. But I think at that point it's just a regular TLB flush, and doesn't need that LAM-specific IPI. But maybe there's some bigger HW serialization that is needed for the LAM bit, I have not looked at that enough to know. Linus