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Date:   Thu, 15 Dec 2022 23:02:58 -0800
From:   Christoph Hellwig <hch@infradead.org>
To:     Palmer Dabbelt <palmer@dabbelt.com>
Cc:     geert@linux-m68k.org, Christoph Hellwig <hch@infradead.org>,
        soc@kernel.org, Conor Dooley <conor@kernel.org>,
        prabhakar.csengg@gmail.com, Arnd Bergmann <arnd@arndb.de>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        aou@eecs.berkeley.edu, magnus.damm@gmail.com, heiko@sntech.de,
        Conor Dooley <conor.dooley@microchip.com>, samuel@sholland.org,
        guoren@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, jszhang@kernel.org,
        Atish Patra <atishp@rivosinc.com>, apatel@ventanamicro.com,
        ajones@ventanamicro.com, nathan@kernel.org,
        philipp.tomsich@vrull.eu, devicetree@vger.kernel.org,
        linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org,
        linux-kernel@vger.kernel.org, biju.das.jz@bp.renesas.com,
        prabhakar.mahadev-lad.rj@bp.renesas.com
Subject: Re: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five
 SoC
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On Thu, Dec 15, 2022 at 01:40:30PM -0800, Palmer Dabbelt wrote:
> Given that we already moved the SiFive one out it seems sane to just start
> with the rest in drivers/soc/$VENDOR.  Looks like it was Christoph's idea to
> do the move, so I'm adding him in case he's got an opinion (and also the SOC
> alias, as that seems generally relevant).

Well, it isn't an integral architecture feature, so it doesn't really
beloing into arch.  Even the irqchip and timer drivers that are more
less architectural are in drivers/ as they aren't really core
architecture code.