Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <8dc05650-428c-2995-a365-d397c92e7a6a@linaro.org>
Date:   Mon, 19 Dec 2022 18:25:16 +0200
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101
 Thunderbird/102.5.1
Subject: Re: [PATCH v5 2/2] clk: qcom: Add QDU1000 and QRU1000 GCC support
Content-Language: en-GB
To:     Melody Olvera <quic_molvera@quicinc.com>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc:     Taniya Das <quic_tdas@quicinc.com>, linux-arm-msm@vger.kernel.org,
        linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20221216230722.21404-1-quic_molvera@quicinc.com>
 <20221216230722.21404-3-quic_molvera@quicinc.com>
From:   Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
In-Reply-To: <20221216230722.21404-3-quic_molvera@quicinc.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Precedence: bulk

On 17/12/2022 01:07, Melody Olvera wrote:
> From: Taniya Das <quic_tdas@quicinc.com>
> 
> Add Global Clock Controller (GCC) support for QDU1000 and QRU1000 SoCs.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
>   drivers/clk/qcom/Kconfig       |    8 +
>   drivers/clk/qcom/Makefile      |    1 +
>   drivers/clk/qcom/gcc-qdu1000.c | 2653 ++++++++++++++++++++++++++++++++
>   3 files changed, 2662 insertions(+)
>   create mode 100644 drivers/clk/qcom/gcc-qdu1000.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 70d43f0a8919..d2e9ff7536f5 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -569,6 +569,14 @@ config QCS_Q6SSTOP_404
>   	  Say Y if you want to use the Q6SSTOP branch clocks of the WCSS clock
>   	  controller to reset the Q6SSTOP subsystem.
>   
> +config QDU_GCC_1000
> +	tristate "QDU1000/QRU1000 Global Clock Controller"
> +	select QCOM_GDSC
> +	help
> +	  Support for the global clock controller on QDU1000 and
> +	  QRU1000 devices. Say Y if you want to use peripheral
> +	  devices such as UART, SPI, I2C, USB, SD, PCIe, etc.
> +
>   config SDM_GCC_845
>   	tristate "SDM845/SDM670 Global Clock Controller"
>   	select QCOM_GDSC
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index f18c446a97ea..c1615c76d3df 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -62,6 +62,7 @@ obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
>   obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
>   obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
>   obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
> +obj-$(CONFIG_QDU_GCC_1000) += gcc-qdu1000.o
>   obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o
>   obj-$(CONFIG_SC_CAMCC_7280) += camcc-sc7280.o
>   obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
> new file mode 100644
> index 000000000000..144073562f8d
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-qdu1000.c
> @@ -0,0 +1,2653 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,qdu1000-gcc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "clk-regmap-phy-mux.h"
> +#include "reset.h"
> +
> +enum {
> +	P_BI_TCXO,
> +	P_GCC_GPLL0_OUT_EVEN,
> +	P_GCC_GPLL0_OUT_MAIN,
> +	P_GCC_GPLL1_OUT_MAIN,
> +	P_GCC_GPLL2_OUT_MAIN,
> +	P_GCC_GPLL3_OUT_MAIN,
> +	P_GCC_GPLL4_OUT_MAIN,
> +	P_GCC_GPLL5_OUT_MAIN,
> +	P_GCC_GPLL6_OUT_MAIN,
> +	P_GCC_GPLL7_OUT_MAIN,
> +	P_GCC_GPLL8_OUT_MAIN,
> +	P_PCIE_0_PHY_AUX_CLK,
> +	P_PCIE_0_PIPE_CLK,
> +	P_SLEEP_CLK,
> +	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
> +};
> +
> +enum {
> +	TCXO_IDX,
> +	SLEEP_CLK_IDX,
> +	PCIE_0_PIPE_CLK_IDX,
> +	PCIE_0_PHY_AUX_CLK_IDX,
> +	USB3_PHY_WRAPPER_PIPE_CLK_IDX,
> +};

Please prefix these names with DT_, so that it's clear that they are 
indices in the device tree.

With that fixed:

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry