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Date:   Mon, 19 Dec 2022 16:51:20 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Saleem Abdulrasool <abdulras@google.com>
Cc:     Palmer Dabbelt <palmer@dabbelt.com>, ben.dooks@codethink.co.uk,
        ndesaulniers@google.com, nathan@kernel.org,
        Paul Walmsley <paul.walmsley@sifive.com>,
        aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: avoid enabling vectorized code generation
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On Mon, Dec 19, 2022 at 07:21:32AM -0800, Saleem Abdulrasool wrote:
> On Fri, Dec 16, 2022 at 6:02 PM Conor Dooley <conor@kernel.org> wrote:
> >
> >
> >
> > On 16 December 2022 12:56:23 GMT-08:00, Saleem Abdulrasool <abdulras@go=
ogle.com> wrote:
> > >On Fri, Dec 16, 2022 at 11:54 AM Palmer Dabbelt <palmer@dabbelt.com> w=
rote:
> > >>
> > >> On Fri, 16 Dec 2022 11:45:21 PST (-0800), ben.dooks@codethink.co.uk =
wrote:
> > >> >
> > >> >
> > >> > On 2022-12-16 18:50, Saleem Abdulrasool wrote:
> > >> >> The compiler is free to generate vectorized operations for zero'i=
ng
> > >> >> memory.  The kernel does not use the vector unit on RISCV, simila=
r to
> > >> >> architectures such as x86 where we use `-mno-mmx` et al to preven=
t the
> > >> >> implicit vectorization.  Perform a similar check for
> > >> >> `-mno-implicit-float` to avoid this on RISC-V targets.
> > >> >
> > >> > I'm not sure if we should be emitting either of the vector or floa=
ting
> > >> > point instrucitons in the kernel without explicitly marking the se=
ction
> > >> > of code which is using them such as specific accelerator blocks.
> > >>
> > >> Yep, we can't let the compiler just blindly enable V or F/D.  V would
> > >> very much break things as we have no support, but even when that's in
> > >> we'll we at roughly the same spot as F/D are now where we need to ha=
ndle
> > >> the lazy save/restore bits.
> > >>
> > >> This looks like an LLVM-only option, I see at least some handling he=
re
> > >>
> > >> https://github.com/llvm/llvm-project/blob/a72883b7612f5c00b592da85ed=
2f1fd81258cc08/clang/lib/Driver/ToolChains/Clang.cpp#L2098
> > >>
> > >> but I don't really know LLVM enough to understand if there's some
> > >> default for `-mimplicit-float` and I can't find anything in the docs.
> > >> If it can be turned on by default and that results in F/D/V instruct=
ions
> > >> then we'll need to explicitly turn it off, and that would need to be
> > >> backported.
> > >
> > >Yes, this is an LLVM option, but I think that the `cc-option` wrapping
> > >should help ensure that we do not break the gcc build.  This only
> > >recently was added to clang, so an older clang would also miss this
> > >flag.  The `-mimplicit-float` is the default AFAIK, which is why we
> > >needed to add this flag in the first place.  Enabling V exposed this,
> > >which is why the commit message mentions vector.
> >
> > You've said "enabling V" in the comment and here.
> > By that, do you mean when V support is enabled in clang or when it is e=
nabled in Linux?
>=20
> Excellent distinction.  I meant enabled in the compiler, enabling it
> in the kernel is not yet possible without the pending patchset.  This
> makes us robust to when that patchset is merged, but in the meantime,
> this protects against the V extension being enabled in the toolchain.

Ah cool. I figured that it was not possible without the vector patchset
but I was not 100% as it was a wee bit vague ;)
Since V will not be enabled without that patchset, I guess this does not
*have* to go as a fix or to stable?

Per the option's name &
https://github.com/llvm/llvm-project/commit/549231d38e10de7371adb85f5452d42=
ad42f4201
it may however be better to backport it anyway, in case implicit use of
fp registers does arrive.

You mentioned the gcc build & gcc-12 is fine:
https://patchwork.kernel.org/project/linux-riscv/patch/20221216185012.23426=
75-1-abdulras@google.com/

Anyway, seems like a sensible addition to me, so:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
I think it may also be good to do:
Link: https://github.com/llvm/llvm-project/commit/549231d38e10de7371adb85f5=
452d42ad42f4201

Thanks,
Conor.


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