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Received: from MN0PR12MB6101.namprd12.prod.outlook.com (2603:10b6:208:3cb::10) by IA0PR12MB7553.namprd12.prod.outlook.com (2603:10b6:208:43f::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.16; Mon, 19 Dec 2022 23:28:14 +0000 Received: from MN0PR12MB6101.namprd12.prod.outlook.com ([fe80::ff3c:2d37:75f3:442a]) by MN0PR12MB6101.namprd12.prod.outlook.com ([fe80::ff3c:2d37:75f3:442a%4]) with mapi id 15.20.5924.016; Mon, 19 Dec 2022 23:28:14 +0000 Message-ID: <420e1f4d-90c1-1887-7d5d-7d2c4b38d2e0@amd.com> Date: Mon, 19 Dec 2022 17:28:11 -0600 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v8 10/13] Documentation: amd-pstate: add amd pstate driver mode introduction Content-Language: en-US To: Perry Yuan , rafael.j.wysocki@intel.com, ray.huang@amd.com, viresh.kumar@linaro.org Cc: Deepak.Sharma@amd.com, Nathan.Fontenot@amd.com, Alexander.Deucher@amd.com, Shimmer.Huang@amd.com, Xiaojian.Du@amd.com, Li.Meng@amd.com, wyes.karny@amd.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221219064042.661122-1-perry.yuan@amd.com> <20221219064042.661122-11-perry.yuan@amd.com> From: "Limonciello, Mario" In-Reply-To: <20221219064042.661122-11-perry.yuan@amd.com> Content-Type: text/plain; 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The AMD P-States mechanism is the more performance and energy > efficiency frequency management method on AMD processors. > > -Kernel Module Options for ``amd-pstate`` > -========================================= > + > +AMD Pstate Driver Operation Modes > +================================= > + > +``amd_pstate`` CPPC has two operation modes: CPPC Autonomous(active) mode and > +CPPC non-autonomous(passive) mode. > +active mode and passive mode can be chosen by different kernel parameters. > +When in Autonomous mode, CPPC ignores requests done in the Desired Performance > +Target register and takes into account only the values set to the Minimum requested > +performance, Maximum requested performance, and Energy Performance Preference > +registers. When Autonomous is disabled, it only considers the Desired Performance Target. > + > +Active Mode > +------------ > + > +``amd_pstate=active`` > + > +This is the low-level firmware control mode which is implemented by ``amd_pstate_epp`` > +driver with ``amd_pstate=active`` passed to the kernel in the command line. > +In this mode, ``amd_pstate_epp`` driver provides a hint to the hardware if software > +wants to bias toward performance (0x0) or energy efficiency (0xff) to the CPPC firmware. > +then CPPC power algorithm will calculate the runtime workload and adjust the realtime > +cores frequency according to the power supply and thermal, core voltage and some other > +hardware conditions. > > Passive Mode > ------------