Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Tue, 20 Dec 2022 21:31:43 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Hal Feng <hal.feng@starfivetech.com>
Cc:     linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Ben Dooks <ben.dooks@sifive.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Linus Walleij <linus.walleij@linaro.org>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110
 device tree
Message-ID: <Y6Ipv0BUummgqNaw@spud>
References: <20221220011247.35560-1-hal.feng@starfivetech.com>
 <20221220011247.35560-7-hal.feng@starfivetech.com>
MIME-Version: 1.0
Content-Type: multipart/signed; micalg=pgp-sha256;
        protocol="application/pgp-signature"; boundary="ObhNkYFiXiedhNNQ"
Content-Disposition: inline
In-Reply-To: <20221220011247.35560-7-hal.feng@starfivetech.com>
Precedence: bulk


--ObhNkYFiXiedhNNQ
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable

On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>=20
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>=20
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---

FWIW, this cpu-map is now the default in linux, so you no longer *need*
to add it for that purpose - but there's obviously no harm in being
explicit for other operating systems etc. (IOW, don't remove it!)

> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu =3D <&S76_0>;
> +				};
> +
> +				core1 {
> +					cpu =3D <&U74_1>;
> +				};
> +
> +				core2 {
> +					cpu =3D <&U74_2>;
> +				};
> +
> +				core3 {
> +					cpu =3D <&U74_3>;
> +				};
> +
> +				core4 {
> +					cpu =3D <&U74_4>;
> +				};
> +			};
> +		};
> +	};

> +		syscrg: clock-controller@13020000 {

For obvious reasons, I cannot apply this until both the clock & pinctrl
bindings are in my tree - but you know that already.

> +			compatible =3D "starfive,jh7110-syscrg";
> +			reg =3D <0x0 0x13020000 0x0 0x10000>;
> +			clocks =3D <&osc>, <&gmac1_rmii_refin>,
> +				 <&gmac1_rgmii_rxin>,
> +				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> +				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> +				 <&tdm_ext>, <&mclk_ext>;

As Krzk asked - are these clocks really all inputs to the SoC?

> +			clock-names =3D "osc", "gmac1_rmii_refin",
> +				      "gmac1_rgmii_rxin",
> +				      "i2stx_bclk_ext", "i2stx_lrck_ext",
> +				      "i2srx_bclk_ext", "i2srx_lrck_ext",
> +				      "tdm_ext", "mclk_ext";
> +			#clock-cells =3D <1>;
> +			#reset-cells =3D <1>;
> +		};
> +
> +		gpio: gpio@13040000 {

> +		gpioa: gpio@17020000 {

Out of curiousity, why gpio & gpioa?

Thanks,
Conor.


--ObhNkYFiXiedhNNQ
Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY6IpvwAKCRB4tDGHoIJi
0rWYAQDTig/t+OM+9hgBx8d3GAyl2YXKCY8myegiWUBmFC6xAQD/aQpZ/dHH5sUO
IXoDliLR2oe/z45FzDkNU6ZSUhqQEAA=
=U8m6
-----END PGP SIGNATURE-----

--ObhNkYFiXiedhNNQ--