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Tue, 20 Dec 2022 21:20:03 +0000 Received: from TYWPR01MB8775.jpnprd01.prod.outlook.com ([fe80::9459:ffa9:a884:8a8e]) by TYWPR01MB8775.jpnprd01.prod.outlook.com ([fe80::9459:ffa9:a884:8a8e%3]) with mapi id 15.20.5924.016; Tue, 20 Dec 2022 21:20:03 +0000 From: Fabrizio Castro To: Krzysztof Kozlowski , Rob Herring CC: Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven , Lee Jones , "linux-gpio@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , Chris Paterson , Biju Das , "linux-renesas-soc@vger.kernel.org" , Laurent Pinchart , Jacopo Mondi Subject: RE: [PATCH 1/5] dt-bindings: gpio: Add RZ/V2M PWC GPIO driver bindings Thread-Topic: [PATCH 1/5] dt-bindings: gpio: Add RZ/V2M PWC GPIO driver bindings Thread-Index: AQHZD0RQEfhgdoTwoUKXW2j4jjmej65tjsOAgAANPzCAARpzgIAIm7FA Date: Tue, 20 Dec 2022 21:20:03 +0000 Message-ID: References: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> <20221213224310.543243-2-fabrizio.castro.jz@renesas.com> <20221214161057.GA1140718-robh@kernel.org> <8199105f-4c67-1af3-65fe-a5c8ddababca@linaro.org> In-Reply-To: <8199105f-4c67-1af3-65fe-a5c8ddababca@linaro.org> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=renesas.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TYWPR01MB8775.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 54b3218f-0380-4fb4-85dd-08dae2cff5c8 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Dec 2022 21:20:03.5700 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: F/R5pUJuGPLDWtstjlqTTMwu4NI2k141zog5Z/H6qIvgqIYKvf7t2MqXFylwQI1ySL1V3tnd1EQJAHOK8oyT5awlPvsjxk+9FsPHdUmTvpg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYWPR01MB9422 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Krzysztof, Thanks for your feedback. > From: Krzysztof Kozlowski > Sent: 15 December 2022 09:49 > To: Fabrizio Castro ; Rob Herring > > Subject: Re: [PATCH 1/5] dt-bindings: gpio: Add RZ/V2M PWC GPIO driver > bindings >=20 > On 14/12/2022 19:26, Fabrizio Castro wrote: > > Hi Rob, > > > > Thanks for your feedback! > > > >> From: Rob Herring > >> Sent: 14 December 2022 16:11 > >> To: Fabrizio Castro > >> Subject: Re: [PATCH 1/5] dt-bindings: gpio: Add RZ/V2M PWC GPIO driver > >> bindings > >> > >> On Tue, Dec 13, 2022 at 10:43:06PM +0000, Fabrizio Castro wrote: > >>> Add dt-bindings document for the RZ/V2M PWC GPIO driver. > >> > >> Bindings are for h/w blocks/devices, not a specific driver. > > > > Apologies, I will reword the changelog in v2. > > > >> > >>> > >>> Signed-off-by: Fabrizio Castro > >>> --- > >>> .../bindings/gpio/renesas,rzv2m-pwc-gpio.yaml | 62 > +++++++++++++++++++ > >>> 1 file changed, 62 insertions(+) > >>> create mode 100644 > >> Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.yaml > >>> > >>> diff --git a/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc= - > >> gpio.yaml b/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc- > >> gpio.yaml > >>> new file mode 100644 > >>> index 000000000000..ecc034d53259 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc- > gpio.yaml > >>> @@ -0,0 +1,62 @@ > >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >>> +%YAML 1.2 > >>> +--- > >>> + > >>> +title: Renesas RZ/V2M External Power Sequence Controller (PWC) GPIO > >>> + > >>> +description: |+ > >>> + The PWC IP found in the RZ/V2M family of chips comes with General- > >> Purpose > >>> + Output pins, alongside the below functions > >>> + - external power supply on/off sequence generation > >>> + - on/off signal generation for the LPDDR4 core power supply > (LPVDD) > >>> + - key input signals processing > >>> + This node uses syscon to map the register used to control the GPIO= s > >>> + (the register map is retrieved from the parent dt-node), and the > node > >> should > >>> + be represented as a sub node of a "syscon", "simple-mfd" node. > >>> + > >>> +maintainers: > >>> + - Fabrizio Castro > >>> + > >>> +properties: > >>> + compatible: > >>> + items: > >>> + - enum: > >>> + - renesas,r9a09g011-pwc-gpio # RZ/V2M > >>> + - renesas,r9a09g055-pwc-gpio # RZ/V2MA > >>> + - const: renesas,rzv2m-pwc-gpio > >>> + > >>> + offset: > >> > >> Too generic of a name. We want any given property name (globally) to > >> have 1 type. With the below comment, this should be replaced with 'reg= ' > >> instead if you have child nodes. > > > > My understanding is that syscon subnodes normally use this name for > exactly > > the same purpose, for example: > > > > > > What am I missing? >=20 > These are generic drivers, so they need offset as they do not match any > specific programming model. You are not making a generic device. Address > offsets are not suitable in most cases for DTS. There are of course > exceptions so you can present reasons why this one is exception. Thanks for the explanation > > > >> > >>> + $ref: /schemas/types.yaml#/definitions/uint32 > >>> + description: | > >>> + Offset in the register map for controlling the GPIOs (in > bytes). > >>> + > >>> + regmap: > >>> + $ref: /schemas/types.yaml#/definitions/phandle > >>> + description: Phandle to the register map node. > >> > >> Looks like GPIO is a sub-function of some other block. Define the > >> binding for that entire block. > > > > That's defined in patch 3 from this series. > > I have sent it as patch 3 because that document references: > > * /schemas/gpio/renesas,rzv2m-pwc-gpio.yaml > > * /schemas/power/reset/renesas,rzv2m-pwc-poweroff.yaml > > Which are defined in this patch and in patch 2 in the series. > > > > Do you want me to move patch 3 to patch 1 in v2? >=20 > We do not want regmap, but proper definition of entire hardware. Will do. I'll drop regmap. >=20 > > > >> GPIO can be either either a function of > >> that node (just add GPIO provider properties) or you can have GPIO > child > >> nodes. Depends on what the entire block looks like to decide. Do you > >> have multiple instances of the GPIO block would be one reason to have > >> child nodes. > > > > From a pure HW point of view, this GPIO block is contained inside the > PWC block > > (as PWC is basically a MFD device), and it only deals with 2 General- > Purpose > > Output pins, both controlled by 1 (and the same) register, therefore th= e > GPIO > > block is only 1 child. > > > > If possible, I would like to keep the functionality offered by the sub- > blocks of > > PWC contained in separated drivers and DT nodes (either non-child nodes > or child > > nodes). >=20 > Driver do not matter for bindings. We talk about regmap field which - as > you explained above - is not needed. Okay, I'll rework, and I'll send v2. Thanks, Fab >=20 >=20 > > > > My understanding is that simple-mfd will automatically probe the > children of the > > simple-mfd node, and also hierarchically it makes sense to me to have > the DT nodes > > of the PWC sub-blocks as children of the "syscon", "simple-mfd" node. I > have found > > other instances of this same architecture in the kernel already (plenty > from NXP/Freescale), > > for example: >=20 > I don't understand. You do not have here simple-mfd and it still does > not explain Rob's comment and regmap. >=20 > > > > etc... > > > > Something like the below could also work, but I don't think it would > represent the > > HW accurately: > > pwc: pwc@a3700000 { > > compatible =3D "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc", > > "syscon", "simple-mfd"; > > reg =3D <0 0xa3700000 0 0x800>; > > }; > > > > pwc-gpio { > > compatible =3D "renesas,r9a09g011-pwc-gpio", > > "renesas,rzv2m-pwc-gpio"; > > regmap =3D <&pwc>; > > gpio-controller; > > #gpio-cells =3D <2>; > > }; > > > > pwc-poweroff { > > compatible =3D "renesas,r9a09g011-pwc-poweroff", > > "renesas,rzv2m-pwc-poweroff"; > > regmap =3D <&pwc>; > > }; > > > > > > I think the below describes things better: > > pwc: pwc@a3700000 { > > compatible =3D "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc", > > "syscon", "simple-mfd"; > > reg =3D <0 0xa3700000 0 0x800>; > > > > gpio { > > compatible =3D "renesas,r9a09g011-pwc-gpio", > > "renesas,rzv2m-pwc-gpio"; > > regmap =3D <&pwc>; >=20 > You speak about two different things. So again - drop regmap. You do not > need it. >=20 > > offset =3D <0x80>; > > gpio-controller; > > #gpio-cells =3D <2>; > > }; > > > > poweroff { > > compatible =3D "renesas,r9a09g011-pwc-poweroff", > > "renesas,rzv2m-pwc-poweroff"; > > regmap =3D <&pwc>; >=20 > Drop regmap. >=20 > > }; > > }; > > >=20 > Best regards, > Krzysztof