Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Tue, 20 Dec 2022 22:31:05 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Hal Feng <hal.feng@starfivetech.com>
Cc:     linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        linux-clk@vger.kernel.org, Palmer Dabbelt <palmer@dabbelt.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 05/11] reset: starfive: Rename "jh7100" to "jh71x0"
 for the common code
Message-ID: <Y6I3qbp34+0Mc4lk@spud>
References: <20221220005054.34518-1-hal.feng@starfivetech.com>
 <20221220005054.34518-6-hal.feng@starfivetech.com>
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On Tue, Dec 20, 2022 at 08:50:48AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>=20
> For the common code will be shared with the StarFive JH7110 SoC.
>=20
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

Label on the tin seems to match the contents.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.

> ---
>  .../reset/starfive/reset-starfive-jh7100.c    |  2 +-
>  .../reset/starfive/reset-starfive-jh71x0.c    | 50 +++++++++----------
>  .../reset/starfive/reset-starfive-jh71x0.h    |  2 +-
>  3 files changed, 27 insertions(+), 27 deletions(-)
>=20
> diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/res=
et/starfive/reset-starfive-jh7100.c
> index 9d7cb4ed8869..5f06e5ae3346 100644
> --- a/drivers/reset/starfive/reset-starfive-jh7100.c
> +++ b/drivers/reset/starfive/reset-starfive-jh7100.c
> @@ -51,7 +51,7 @@ static int __init jh7100_reset_probe(struct platform_de=
vice *pdev)
>  	if (IS_ERR(base))
>  		return PTR_ERR(base);
> =20
> -	return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
> +	return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
>  					      base + JH7100_RESET_ASSERT0,
>  					      base + JH7100_RESET_STATUS0,
>  					      jh7100_reset_asserted,
> diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/res=
et/starfive/reset-starfive-jh71x0.c
> index ee8c28f9bcb5..1f201c612583 100644
> --- a/drivers/reset/starfive/reset-starfive-jh71x0.c
> +++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: GPL-2.0-or-later
>  /*
> - * Reset driver for the StarFive JH7100 SoC
> + * Reset driver for the StarFive JH71X0 SoCs
>   *
>   * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
>   */
> @@ -13,7 +13,7 @@
>  #include <linux/reset-controller.h>
>  #include <linux/spinlock.h>
> =20
> -struct jh7100_reset {
> +struct jh71x0_reset {
>  	struct reset_controller_dev rcdev;
>  	/* protect registers against concurrent read-modify-write */
>  	spinlock_t lock;
> @@ -22,16 +22,16 @@ struct jh7100_reset {
>  	const u64 *asserted;
>  };
> =20
> -static inline struct jh7100_reset *
> -jh7100_reset_from(struct reset_controller_dev *rcdev)
> +static inline struct jh71x0_reset *
> +jh71x0_reset_from(struct reset_controller_dev *rcdev)
>  {
> -	return container_of(rcdev, struct jh7100_reset, rcdev);
> +	return container_of(rcdev, struct jh71x0_reset, rcdev);
>  }
> =20
> -static int jh7100_reset_update(struct reset_controller_dev *rcdev,
> +static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
>  			       unsigned long id, bool assert)
>  {
> -	struct jh7100_reset *data =3D jh7100_reset_from(rcdev);
> +	struct jh71x0_reset *data =3D jh71x0_reset_from(rcdev);
>  	unsigned long offset =3D BIT_ULL_WORD(id);
>  	u64 mask =3D BIT_ULL_MASK(id);
>  	void __iomem *reg_assert =3D data->assert + offset * sizeof(u64);
> @@ -60,34 +60,34 @@ static int jh7100_reset_update(struct reset_controlle=
r_dev *rcdev,
>  	return ret;
>  }
> =20
> -static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
> +static int jh71x0_reset_assert(struct reset_controller_dev *rcdev,
>  			       unsigned long id)
>  {
> -	return jh7100_reset_update(rcdev, id, true);
> +	return jh71x0_reset_update(rcdev, id, true);
>  }
> =20
> -static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
> +static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev,
>  				 unsigned long id)
>  {
> -	return jh7100_reset_update(rcdev, id, false);
> +	return jh71x0_reset_update(rcdev, id, false);
>  }
> =20
> -static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
> +static int jh71x0_reset_reset(struct reset_controller_dev *rcdev,
>  			      unsigned long id)
>  {
>  	int ret;
> =20
> -	ret =3D jh7100_reset_assert(rcdev, id);
> +	ret =3D jh71x0_reset_assert(rcdev, id);
>  	if (ret)
>  		return ret;
> =20
> -	return jh7100_reset_deassert(rcdev, id);
> +	return jh71x0_reset_deassert(rcdev, id);
>  }
> =20
> -static int jh7100_reset_status(struct reset_controller_dev *rcdev,
> +static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
>  			       unsigned long id)
>  {
> -	struct jh7100_reset *data =3D jh7100_reset_from(rcdev);
> +	struct jh71x0_reset *data =3D jh71x0_reset_from(rcdev);
>  	unsigned long offset =3D BIT_ULL_WORD(id);
>  	u64 mask =3D BIT_ULL_MASK(id);
>  	void __iomem *reg_status =3D data->status + offset * sizeof(u64);
> @@ -96,25 +96,25 @@ static int jh7100_reset_status(struct reset_controlle=
r_dev *rcdev,
>  	return !((value ^ data->asserted[offset]) & mask);
>  }
> =20
> -static const struct reset_control_ops jh7100_reset_ops =3D {
> -	.assert		=3D jh7100_reset_assert,
> -	.deassert	=3D jh7100_reset_deassert,
> -	.reset		=3D jh7100_reset_reset,
> -	.status		=3D jh7100_reset_status,
> +static const struct reset_control_ops jh71x0_reset_ops =3D {
> +	.assert		=3D jh71x0_reset_assert,
> +	.deassert	=3D jh71x0_reset_deassert,
> +	.reset		=3D jh71x0_reset_reset,
> +	.status		=3D jh71x0_reset_status,
>  };
> =20
> -int reset_starfive_jh7100_register(struct device *dev, struct device_nod=
e *of_node,
> +int reset_starfive_jh71x0_register(struct device *dev, struct device_nod=
e *of_node,
>  				   void __iomem *assert, void __iomem *status,
>  				   const u64 *asserted, unsigned int nr_resets,
>  				   struct module *owner)
>  {
> -	struct jh7100_reset *data;
> +	struct jh71x0_reset *data;
> =20
>  	data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
>  	if (!data)
>  		return -ENOMEM;
> =20
> -	data->rcdev.ops =3D &jh7100_reset_ops;
> +	data->rcdev.ops =3D &jh71x0_reset_ops;
>  	data->rcdev.owner =3D owner;
>  	data->rcdev.nr_resets =3D nr_resets;
>  	data->rcdev.dev =3D dev;
> @@ -127,4 +127,4 @@ int reset_starfive_jh7100_register(struct device *dev=
, struct device_node *of_no
> =20
>  	return devm_reset_controller_register(dev, &data->rcdev);
>  }
> -EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);
> +EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
> diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/res=
et/starfive/reset-starfive-jh71x0.h
> index 1fc5a648c8d8..ac9e80dd3f59 100644
> --- a/drivers/reset/starfive/reset-starfive-jh71x0.h
> +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
> @@ -6,7 +6,7 @@
>  #ifndef __RESET_STARFIVE_JH71X0_H
>  #define __RESET_STARFIVE_JH71X0_H
> =20
> -int reset_starfive_jh7100_register(struct device *dev, struct device_nod=
e *of_node,
> +int reset_starfive_jh71x0_register(struct device *dev, struct device_nod=
e *of_node,
>  				   void __iomem *assert, void __iomem *status,
>  				   const u64 *asserted, unsigned int nr_resets,
>  				   struct module *owner);
> --=20
> 2.38.1
>=20
>=20

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