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[2620:137:e000::1:20]) by mx.google.com with ESMTP id q193-20020a632aca000000b00477c8f621ffsi15837266pgq.657.2022.12.20.19.51.42; Tue, 20 Dec 2022 19:51:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=JUwXgzvw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234428AbiLUDo3 (ORCPT + 69 others); Tue, 20 Dec 2022 22:44:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234408AbiLUDoZ (ORCPT ); Tue, 20 Dec 2022 22:44:25 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 204AC1EAF8; Tue, 20 Dec 2022 19:44:19 -0800 (PST) X-UUID: 460de0934efa4a9caaa3396820578959-20221221 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BdUxFNzQWMfOlVhrDimIZG6FxQhwlQm+RNutrnpG9Yg=; b=JUwXgzvw9n9ei/JuSaHqhdgdmtnYgs85ysRFyh4p6Zs1z8lpL9PDWrCc5Gww5BTV06xiduuWAn2iJABOVXBnVHNUEpqnXsLwZFRpMHS/6Xpp8b9Rvxm+YCYWBEJslNDHtlrKV0s8UgG35WuCvd4PmuEoGQavAOkmZ2ukZBlqZ4o=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:f23b3825-25b0-4bca-9c0f-13417be2578f,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:dcaaed0,CLOUDID:39965952-dd49-462e-a4be-2143a3ddc739,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 460de0934efa4a9caaa3396820578959-20221221 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1961216382; Wed, 21 Dec 2022 11:44:15 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 21 Dec 2022 11:44:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 21 Dec 2022 11:44:13 +0800 From: Allen-KH Cheng To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chun-Jie Chen , "Stephen Boyd" , Ikjoon Jang CC: , , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH v2 5/6] dt-bindings: arm: mediatek: Add missing power-domains property Date: Wed, 21 Dec 2022 11:44:06 +0800 Message-ID: <20221221034407.19605-6-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221221034407.19605-1-allen-kh.cheng@mediatek.com> References: <20221221034407.19605-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The "mediatek,mt8192-scp_adsp" binding requires a power domain to be specified. Fixes: 4a803990aeb1 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock") Signed-off-by: Allen-KH Cheng --- .../arm/mediatek/mediatek,mt8192-clock.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml index b57cc2e69efb..ce8dd2bfb533 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml @@ -40,6 +40,9 @@ properties: reg: maxItems: 1 + power-domains: + maxItems: 1 + '#clock-cells': const: 1 @@ -47,13 +50,27 @@ required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8192-scp_adsp + then: + required: + - power-domains + additionalProperties: false examples: - | + #include + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0x10720000 0x1000>; + power-domains = <&spm MT8192_POWER_DOMAIN_ADSP>; #clock-cells = <1>; }; -- 2.18.0