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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Wed, 21 Dec 2022 21:06:22 +0000
Message-ID: <CA+V-a8tqvY+Nj391j+zJO21Q=47pyFR1SkDLH-hmJephcorY3g@mail.gmail.com>
Subject: Re: [PATCH v2 1/9] dt-bindings: interrupt-controller:
 renesas,rzg2l-irqc: Document RZ/G2UL SoC
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

Hi Geert,

Thank you for the review.

On Wed, Dec 21, 2022 at 12:37 PM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Dec 21, 2022 at 1:03 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC
> > is almost identical to one found on the RZ/G2L SoC the only difference
> > being it can support BUS_ERR_INT for which it has additional registers.
> > Hence new generic compatible string "renesas,rzg2ul-irqc" is added for
> > RZ/G2UL SoC.
> >
> > Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC
> > interrupt-names property is added so that we can parse them based on
> > names.
> >
> > While at it updated the example node to four spaces and added
> > interrupt-names property.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1- > v2
> > * Dropped RB tags
> > * Added generic compatible string for rzg2ul
> > * Added interrupt-names
> > * Added checks for RZ/G2UL to make sure interrupts are 42 and interrupt-names
> > * Updated example node with interrupt-names
> > * Used 4 spaces for example node
>
> Thanks for the update!
>
> > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > @@ -19,16 +19,19 @@ description: |
> >      - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
> >        stand-up edge detection interrupts)
> >
> > -allOf:
> > -  - $ref: /schemas/interrupt-controller.yaml#
> > -
> >  properties:
> >    compatible:
> > -    items:
> > -      - enum:
> > -          - renesas,r9a07g044-irqc    # RZ/G2{L,LC}
> > -          - renesas,r9a07g054-irqc    # RZ/V2L
> > -      - const: renesas,rzg2l-irqc
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - renesas,r9a07g044-irqc    # RZ/G2{L,LC}
> > +              - renesas,r9a07g054-irqc    # RZ/V2L
> > +          - const: renesas,rzg2l-irqc
> > +
> > +      - items:
> > +          - enum:
> > +              - renesas,r9a07g043u-irqc   # RZ/G2UL
> > +          - const: renesas,rzg2ul-irqc
>
> I'm not sure it's worth splitting into RZ/G2L and RZ/G2UL alike
> variants, and adding the "renesas,rzg2ul-irqc" family-specific
> compatible value.  You can easily handle the difference by the presence
> (or absence) of the "bus-err" interrupt source.
>
Yes, the only reason to add "renesas,rzg2ul-irqc" is to differentiate
RZ/Five later. I have not worked out on how this driver will work in
case of RZ/Five yet with PLIC (as we sifive plic driver as a chained
handler and then we have the RISC-V intc driver). If you insist I can
drop it for now and then later when we add RZ/FIve we could add a
check for compat string maybe?

> I understand there "renesas,r9a07g043f-irqc" will be added later to
> support RZ/Five?
>
Yes.

Cheers,
Prabhakar