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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d19-20020a056a0010d300b0055f8c0018b0si291550pfu.288.2022.12.22.02.37.12; Thu, 22 Dec 2022 02:37:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235160AbiLVKQR (ORCPT + 67 others); Thu, 22 Dec 2022 05:16:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235033AbiLVKQP (ORCPT ); Thu, 22 Dec 2022 05:16:15 -0500 Received: from m-r1.th.seeweb.it (m-r1.th.seeweb.it [5.144.164.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2074C6462 for ; Thu, 22 Dec 2022 02:16:14 -0800 (PST) Received: from SoMainline.org (94-209-172-39.cable.dynamic.v4.ziggo.nl [94.209.172.39]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 4C1B420449; Thu, 22 Dec 2022 11:16:12 +0100 (CET) Date: Thu, 22 Dec 2022 11:16:11 +0100 From: Marijn Suijten To: Krzysztof Kozlowski Cc: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: Re: [PATCH] dt-bindings: arm-smmu: disallow clocks when not used Message-ID: <20221222101611.nwt5arux2hcvvtvf@SoMainline.org> References: <20221222092355.74586-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221222092355.74586-1-krzysztof.kozlowski@linaro.org> X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Is this missing a cc to linux-arm-msm? On 2022-12-22 10:23:55, Krzysztof Kozlowski wrote: > Disallow clocks for variants other than: > 1. SMMUs with platform-specific compatibles which list explicit clocks > and clock-names, > 2. SMMUs using only generic compatibles, e.g. arm,mmu-500, which have a > variable clocks on different implementations. > > This requires such variants with platform-specific compatible, to > explicitly list the clocks or omit them, making the binding more > constraint. > > Signed-off-by: Krzysztof Kozlowski Reviewed-by: Marijn Suijten But... > --- > > Cc: Marijn Suijten > Cc: Dmitry Baryshkov > Cc: Konrad Dybcio > --- > .../devicetree/bindings/iommu/arm,smmu.yaml | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 895ec8418465..0d88395e43ad 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -367,6 +367,34 @@ allOf: > - description: interface clock required to access smmu's registers > through the TCU's programming interface. > > + # Disallow clocks for all other platforms with specific compatibles > + - if: > + properties: > + compatible: > + contains: > + enum: > + - cavium,smmu-v2 > + - marvell,ap806-smmu-500 > + - nvidia,smmu-500 > + - qcom,qcm2290-smmu-500 > + - qcom,qdu1000-smmu-500 > + - qcom,sc7180-smmu-500 Hmm, sc7280 has two SMMUs. The one for Adreno has clocks and a PD, the one for APPS has neither. Same story on sm8[12]50. Aren't those going to trip up the other `if` that requires clocks in both scenarios? Note that the Adreno SMMUs have (or will get when we/Konrad submit support for it) the "qcom,adreno-smmu" compatible to distinguish them. - Marijn > + - qcom,sc8180x-smmu-500 > + - qcom,sc8280xp-smmu-500 > + - qcom,sdm670-smmu-500 > + - qcom,sdm845-smmu-500 > + - qcom,sdx55-smmu-500 > + - qcom,sdx65-smmu-500 > + - qcom,sm6115-smmu-500 > + - qcom,sm6350-smmu-500 > + - qcom,sm6375-smmu-500 > + - qcom,sm8350-smmu-500 > + - qcom,sm8450-smmu-500 > + then: > + properties: > + clock-names: false > + clocks: false > + > - if: > properties: > compatible: > -- > 2.34.1 >