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[209.85.219.181]) by smtp.gmail.com with ESMTPSA id r17-20020ae9d611000000b00704c62638f4sm8597qkk.89.2022.12.22.04.51.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Dec 2022 04:51:54 -0800 (PST) Received: by mail-yb1-f181.google.com with SMTP id e141so1840398ybh.3; Thu, 22 Dec 2022 04:51:53 -0800 (PST) X-Received: by 2002:a25:d243:0:b0:702:90b4:2e24 with SMTP id j64-20020a25d243000000b0070290b42e24mr398540ybg.365.1671713513672; Thu, 22 Dec 2022 04:51:53 -0800 (PST) MIME-Version: 1.0 References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221221000242.340202-5-prabhakar.mahadev-lad.rj@bp.renesas.com> <86o7rxawhn.wl-maz@kernel.org> In-Reply-To: From: Geert Uytterhoeven Date: Thu, 22 Dec 2022 13:51:41 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 4/9] irqchip: irq-renesas-rzg2l: Add support for RZ/G2UL SoC To: "Lad, Prabhakar" Cc: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Prabhakar, On Thu, Dec 22, 2022 at 12:50 PM Lad, Prabhakar wrote: > On Wed, Dec 21, 2022 at 12:18 PM Geert Uytterhoeven > wrote: > > On Wed, Dec 21, 2022 at 11:20 AM Marc Zyngier wrote: > > > On Wed, 21 Dec 2022 00:02:37 +0000, > > > Prabhakar wrote: > > > > > > > > From: Lad Prabhakar > > > > > > > > The IRQC block on RZ/G2UL SoC is almost identical to one found on the > > > > RZ/G2L SoC the only difference being it can support BUS_ERR_INT for > > > > which it has additional registers. > > > > > > > > This patch adds a new entry for "renesas,rzg2ul-irqc" compatible string > > > > and now that we have interrupt-names property the driver code parses the > > > > interrupts based on names and for backward compatibility we fallback to > > > > parse interrupts based on index. > > > > > > > > For now we will be using rzg2l_irqc_init() as a callback for RZ/G2UL SoC > > > > too and in future when the interrupt handler will be registered for > > > > BUS_ERR_INT we will have to implement a new callback. > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > +/* Parse hierarchy domain interrupts ie only IRQ0-7 and TINT0-31 */ > > > > +static int rzg2l_irqc_parse_hierarchy_interrupts(struct rzg2l_irqc_priv *priv, > > > > + struct device_node *np) > > > > +{ > > > > + struct property *pp; > > > > unsigned int i; > > > > int ret; > > > > > > > > + /* > > > > + * first check if interrupt-names property exists if so parse them by name > > > > + * or else parse them by index for backward compatibility. > > > > + */ > > > > + pp = of_find_property(np, "interrupt-names", NULL); > > > > + if (pp) { > > > > + char *irq_name; > > > > + > > > > + /* parse IRQ0-7 */ > > > > + for (i = 0; i < IRQC_IRQ_COUNT; i++) { > > > > + irq_name = kasprintf(GFP_KERNEL, "irq%d", i); > > > > %u > > > Ok. > > > > > + if (!irq_name) > > > > + return -ENOMEM; > > > > + > > > > + ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, i); > > > > > > Am I the only one that find it rather odd to construct a name from an > > > index, only to get another index back? > > > > The issue is that there are two number ranges ("irq%u" and "tint%u"), > > stored in a single interrupts property. > > > > An alternative solution would be to get rid of the "interrupt-names", > > and use two separate prefixed interrupts properties instead, like is > > common for e.g. gpios: "irq-interrupts" and "tint-interrupts". > > > Maybe I will read all the interrupts based on index only for all the > SoCs and we still add interrupt-names in dt bindings with the > dt_binding check we can make sure all the interrupts for each SoC > exist in the DT and the driver still reads them based on index. Does > that sound good? Sure, sounds fine. You can postpone parsing interrupt-names in the driver (until a new SoC arrives that uses a different number of IRQ or TINT interrupts). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds