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Message-ID: <9dec25fa-7bce-a715-b63e-0a71b5743e3d@linaro.org>
Date:   Thu, 22 Dec 2022 15:06:53 +0100
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Subject: Re: [PATCH v3 0/2] adds corstone500 device tree
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To:     Emekcan Aras <emekcan.aras@arm.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk+dt@kernel.org>,
        Liviu Dudau <liviu.dudau@arm.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Sudeep Holla <sudeep.holla@arm.com>,
        Miguel Silva <rui.silva@linaro.org>
Cc:     linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20221222123244.147238-1-emekcan.aras@arm.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <20221222123244.147238-1-emekcan.aras@arm.com>
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On 22/12/2022 13:32, Emekcan Aras wrote:
> Adds device tree and correspondent binding for ARM Corstone500 reference 
> solution. 
> 
> Thanks for the comments, and sorry for the late reply. Most of the comments are
> addressed except one.
> 
> @Krzysztof Kozlowski: Thanks a lot for the comments. I've tried to fixed all of 
> them. Just have one question regarding having no dtsi or compatible platform.
> Corstone500 is a reference hardware design, however there is no silicon solution
> from it yet. And from device tree perspective, both FPGA and FVP (virtual 
> platform) implementations are identical(same addresses and same nodes, etc.).
> So we didn't want to create a seperate dtsi file. What would you recommend here
> ? Can you point me to a device tree from a similar platform?

Corstone1000 was accepted that way, so it is fine. I am just surprised
that if you are going to have silicons with it, there is no common
compatible and no shared DTSI.

What do you expect from customer? Re-implement and copy most of your DTS?

Best regards,
Krzysztof