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Message-ID: <041b77e0-40c5-e724-e5d9-f1da64d5e684@kernel.org>
Date:   Thu, 22 Dec 2022 16:21:35 +0100
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Subject: Re: [RFC PATCH 6/7] ARM: dts: stm32: add ETZPC as a system bus for
 STM32MP15x boards
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To:     Gatien CHEVALLIER <gatien.chevallier@foss.st.com>,
        alexandre.torgue@foss.st.com, robh+dt@kernel.org,
        Oleksii_Moisieiev@epam.com, linus.walleij@linaro.org,
        gregkh@linuxfoundation.org
Cc:     linux-stm32@st-md-mailman.stormreply.com,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        loic.pallardy@st.com, devicetree@vger.kernel.org,
        mark.rutland@arm.com, arnd@arndb.de
References: <20221221173055.11719-1-gatien.chevallier@foss.st.com>
 <20221221173055.11719-7-gatien.chevallier@foss.st.com>
 <2e7c901c-e322-ded6-b170-6d2436d74c0f@kernel.org>
 <0bff5b2d-2837-57cb-5434-58158acc1483@foss.st.com>
From:   Krzysztof Kozlowski <krzk@kernel.org>
In-Reply-To: <0bff5b2d-2837-57cb-5434-58158acc1483@foss.st.com>
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On 22/12/2022 15:42, Gatien CHEVALLIER wrote:
> Hello,
> 
> 
> On 12/22/22 11:30, Krzysztof Kozlowski wrote:
>> On 21/12/2022 18:30, Gatien Chevallier wrote:
>>> The STM32 System Bus is an internal bus on which devices are connected.
>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>> and control access to the peripherals connected on it.
>>>
>>> For more information on which peripheral is securable, please read
>>> the STM32MP15 reference manual.
>>>
>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>> ---
>>>   arch/arm/boot/dts/stm32mp151.dtsi | 2737 +++++++++++++++--------------
>>>   1 file changed, 1406 insertions(+), 1331 deletions(-)
>>>   
>>> -		lptimer1: timer@40009000 {
>>> +		etzpc: etzpc@5c007000 {
>>
>> Node names should be generic.
>> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> 
> Will change to etzpc: bus@5c007000 in V3
> 
>>
>>> +			compatible = "st,stm32mp15-sys-bus";
>>> +			reg = <0x5c007000 0x400>;
>>>   			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			compatible = "st,stm32-lptimer";
>>> -			reg = <0x40009000 0x400>;
>>> -			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc LPTIM1_K>;
>>> -			clock-names = "mux";
>>> -			wakeup-source;
>>> -			status = "disabled";
>>
>> Why entire bus is disabled? What resources do you miss?
> 
> Here, I did not want to modify the status of the nodes in the device 

By making it disabled you actually modify the status of any enabled
node. By making it enabled you do not cause any change.

> tree. Nodes that are default enabled in the SoC device tree stay enabled 
> and vice-versa.

No, because parent is disabled.

> IMO think this patch should not include these kind of 
> changes in its scope. I describe the bus and the peripherals connected 
> to it, nothing more :)

I am not proposing to change existing nodes. I am asking why new node is
being disabled (because it is a new node, isn't it?).

Best regards,
Krzysztof