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From:   Joel Fernandes <joel@joelfernandes.org>
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Subject: Re: [RFC 0/2] srcu: Remove pre-flip memory barrier
Date:   Thu, 22 Dec 2022 13:19:06 -0500
Message-Id: <71C23049-158C-4E43-A54F-714640393682@joelfernandes.org>
References: <20221222164302.GP4001@paulmck-ThinkPad-P17-Gen-1>
Cc:     Frederic Weisbecker <frederic@kernel.org>,
        Mathieu Desnoyers <mathieu.desnoyers@efficios.com>,
        linux-kernel@vger.kernel.org,
        Josh Triplett <josh@joshtriplett.org>,
        Lai Jiangshan <jiangshanlai@gmail.com>, rcu@vger.kernel.org,
        Steven Rostedt <rostedt@goodmis.org>
In-Reply-To: <20221222164302.GP4001@paulmck-ThinkPad-P17-Gen-1>
To:     paulmck@kernel.org
Precedence: bulk


> On Dec 22, 2022, at 11:43 AM, Paul E. McKenney <paulmck@kernel.org> wrote:=

>=20
> =EF=BB=BFOn Thu, Dec 22, 2022 at 01:40:10PM +0100, Frederic Weisbecker wro=
te:
>>> On Wed, Dec 21, 2022 at 12:11:42PM -0500, Mathieu Desnoyers wrote:
>>> On 2022-12-21 06:59, Frederic Weisbecker wrote:
>>>>> On Tue, Dec 20, 2022 at 10:34:19PM -0500, Mathieu Desnoyers wrote:
>>> [...]
>>>>>=20
>>>>> The memory ordering constraint I am concerned about here is:
>>>>>=20
>>>>>  * [...] In addition,
>>>>>  * each CPU having an SRCU read-side critical section that extends bey=
ond
>>>>>  * the return from synchronize_srcu() is guaranteed to have executed a=

>>>>>  * full memory barrier after the beginning of synchronize_srcu() and b=
efore
>>>>>  * the beginning of that SRCU read-side critical section. [...]
>>>>>=20
>>>>> So if we have a SRCU read-side critical section that begins after the b=
eginning
>>>>> of synchronize_srcu, but before its first memory barrier, it would mis=
s the
>>>>> guarantee that the full memory barrier is issued before the beginning o=
f that
>>>>> SRCU read-side critical section. IOW, that memory barrier needs to be a=
t the
>>>>> very beginning of the grace period.
>>>>=20
>>>> I'm confused, what's wrong with this ?
>>>>=20
>>>> UPDATER                  READER
>>>> -------                  ------
>>>> STORE X =3D 1              STORE srcu_read_lock++
>>>> // rcu_seq_snap()        smp_mb()
>>>> smp_mb()                 READ X
>>>> // scans
>>>> READ srcu_read_lock
>>>=20
>>> What you refer to here is only memory ordering of the store to X and loa=
d
>>> from X wrt loading/increment of srcu_read_lock, which is internal to the=

>>> srcu implementation. If we really want to model the provided high-level
>>> memory ordering guarantees, we should consider a scenario where SRCU is u=
sed
>>> for its memory ordering properties to synchronize other variables.
>>>=20
>>> I'm concerned about the following Dekker scenario, where synchronize_src=
u()
>>> and srcu_read_lock/unlock would be used instead of memory barriers:
>>>=20
>>> Initial state: X =3D 0, Y =3D 0
>>>=20
>>> Thread A                   Thread B
>>> ---------------------------------------------
>>> STORE X =3D 1                STORE Y =3D 1
>>> synchronize_srcu()
>>>                           srcu_read_lock()
>>>                           r1 =3D LOAD X
>>>                           srcu_read_unlock()
>>> r0 =3D LOAD Y
>>>=20
>>> BUG_ON(!r0 && !r1)
>>>=20
>>> So in the synchronize_srcu implementation, there appears to be two
>>> major scenarios: either srcu_gp_start_if_needed starts a gp or expedited=
 gp,
>>> or it uses an already started gp/expedited gp. When snapshotting with
>>> rcu_seq_snap, the fact that the memory barrier is after the ssp->srcu_gp=
_seq
>>> load means that it does not order prior memory accesses before that load=
.
>>> This sequence value is then used to identify which gp_seq to wait for wh=
en
>>> piggy-backing on another already-started gp. I worry about reordering
>>> between STORE X =3D 1 and load of ssp->srcu_gp_seq, which is then used t=
o
>>> piggy-back on an already-started gp.
>>>=20
>>> I suspect that the implicit barrier in srcu_read_lock() invoked at the
>>> beginning of srcu_gp_start_if_needed() is really the barrier that makes
>>> all this behave as expected. But without documentation it's rather hard t=
o
>>> follow.
>>=20
>> Oh ok I see now. It might be working that way by accident or on forgotten=

>> purpose. In any case, we really want to add a comment above that
>> __srcu_read_lock_nmisafe() call.
>=20
> Another test for the safety (or not) of removing either D or E is
> to move that WRITE_ONCE() to follow (or, respectively, precede) the
> adjacent scans.

Good idea, though I believe the MBs that the above talk about are not the fl=
ip ones. They are the ones in synchronize_srcu() beginning and end, that ord=
er with respect to grace period start and end.

So that (flipping MBs) is unrelated, or did I miss something?

Thanks.


>=20
>                            Thanx, Paul