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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id y15-20020a056870418f00b00144e18d8525sm592152oac.25.2022.12.22.11.01.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 11:01:41 -0800 (PST) Received: (nullmailer pid 1911711 invoked by uid 1000); Thu, 22 Dec 2022 19:01:41 -0000 Date: Thu, 22 Dec 2022 13:01:41 -0600 From: Rob Herring To: Manivannan Sadhasivam Cc: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, bhelgaas@google.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/3] dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties Message-ID: <20221222190141.GA1908434-robh@kernel.org> References: <20221222133123.50676-1-manivannan.sadhasivam@linaro.org> <20221222133123.50676-3-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221222133123.50676-3-manivannan.sadhasivam@linaro.org> X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Dec 22, 2022 at 07:01:22PM +0530, Manivannan Sadhasivam wrote: > The Qcom PCIe controller is capable of using either internal MSI controller > or the external GIC-ITS for receiving the MSIs from endpoint devices. > Currently, the binding only documents the internal MSI implementation. > > Let's document the GIC-ITS imeplementation by making use of msi-map and > msi-map-mask properties. Only one of the implementation should be used > at a time. Isn't that up to the OS to decide? Some versions may not support MSIs. What about legacy interrupts? Don't you need to keep the interrupt properties for them? > Signed-off-by: Manivannan Sadhasivam > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 02450fb26bb9..10fec6a7abfc 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -104,14 +104,20 @@ required: > - compatible > - reg > - reg-names > - - interrupts > - - interrupt-names > - - "#interrupt-cells" > - interrupt-map-mask > - interrupt-map > - clocks > - clock-names > > +oneOf: > + - required: > + - interrupts > + - interrupt-names > + - "#interrupt-cells" > + - required: > + - msi-map > + - msi-map-mask > + > allOf: > - $ref: /schemas/pci/pci-bus.yaml# > - if: > -- > 2.25.1 > >