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From:   Apurva Nandan <a-nandan@ti.com>
To:     Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
        Tero Kristo <kristo@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-gpio@vger.kernel.org>
CC:     Apurva Nandan <a-nandan@ti.com>, Hari Nagalla <hnagalla@ti.com>
Subject: [PATCH v4 0/4] Add initial support for J784S4 SoC
Date:   Fri, 23 Dec 2022 02:15:41 +0530
Message-ID: <20221222204545.45281-1-a-nandan@ti.com>
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The J784S4 SoC belongs to the K3 Multicore SoC architecture
platform, providing advanced system integration in automotive,
ADAS and industrial applications requiring AI at the network edge.
This SoC extends the K3 Jacinto 7 family of SoCs with focus on
raising performance and integration while providing interfaces,
memory architecture and compute performance for multi-sensor, high
concurrency applications.

Some highlights of this SoC are:
* Up to 8 Cortex-A72s, four clusters of lockstep capable dual Cortex-R5F MCUs,
  4 C7x floating point vector DSPs with Matrix Multiply Accelerator(MMA) for
  deep learning and CNN.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
  and Motion Processing Accelerator (DMPAC)
* Three CSI2.0 4L RX plus two CSI2.0 4L TX, two DSI Tx, one eDP/DP and one
  DPI interface.
* Integrated gigabit ethernet switch, up to 8 ports (TDA4VH), two ports
  support 10Gb USXGMII; Two 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role
  device subsystems, Up to 20 MCANs, among other peripherals.

See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022)
for further details: http://www.ti.com/lit/zip/spruj52

bootlog: https://rentry.co/gbefx/raw

Changes in v4:
- Removed ti,sci-dev-id from main_navss and mcu_navss, also changed their
  compatibles to "simple-bus"
- Removed status = "disabled" from phy_gmii_sel and cpts@3d000
- Removed empty chosen {} from k3-j784s4.dtsi

Changes in v3:
- Enabled hwspinlock, main_ringacc, main_udmap, cpts, and mcu_navss in
  the dtsi
- Removed alignment in secure_ddr optee
- Changed the assigned clock parent in main and mcu cpts to main pll0, hsdiv6
  from pll3, hsdiv1
- Removed few signed-off by
- Formatting fixes at some places
- Corrected link to EVM board schmatics in the commit

Changes in v2:
- Disabled all the IPs that are not mandatory for booting up the SoC by
  default in the dtsi, and thus this gives a minimal SoC boot devicetree.
- Moved no-1-8-v property from the k3-j784s4-evm.dts file to
  k3-j784s4-main.dtsi file.
- Naming changes (hwlock, regulator) and commit description changes.
- Added device specific compatible for j721e system controller.
- Dropped bootargs completely.

Apurva Nandan (4):
  dt-bindings: arm: ti: Add bindings for J784s4 SoC
  dt-bindings: pinctrl: k3: Introduce pinmux definitions for J784s4
  arm64: dts: ti: Add initial support for J784S4 SoC
  arm64: dts: ti: Add support for J784S4 EVM board

 .../devicetree/bindings/arm/ti/k3.yaml        |    6 +
 arch/arm64/boot/dts/ti/Makefile               |    2 +
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts      |  196 ++++
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi    | 1007 +++++++++++++++++
 .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi     |  311 +++++
 arch/arm64/boot/dts/ti/k3-j784s4.dtsi         |  284 +++++
 include/dt-bindings/pinctrl/k3.h              |    3 +
 7 files changed, 1809 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
 create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4.dtsi

-- 
2.34.1