Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761273AbXHQFGE (ORCPT ); Fri, 17 Aug 2007 01:06:04 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755266AbXHQFFL (ORCPT ); Fri, 17 Aug 2007 01:05:11 -0400 Received: from ozlabs.org ([203.10.76.45]:53239 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754682AbXHQFFI (ORCPT ); Fri, 17 Aug 2007 01:05:08 -0400 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <18117.11376.111737.891134@cargo.ozlabs.ibm.com> Date: Fri, 17 Aug 2007 15:04:48 +1000 From: Paul Mackerras To: Herbert Xu Cc: Stefan Richter , Satyam Sharma , Christoph Lameter , "Paul E. McKenney" , Chris Snook , Linux Kernel Mailing List , linux-arch@vger.kernel.org, Linus Torvalds , netdev@vger.kernel.org, Andrew Morton , ak@suse.de, heiko.carstens@de.ibm.com, davem@davemloft.net, schwidefsky@de.ibm.com, wensong@linux-vs.org, horms@verge.net.au, wjiang@resilience.com, cfriesen@nortel.com, zlynx@acm.org, rpjday@mindspring.com, jesper.juhl@gmail.com, segher@kernel.crashing.org Subject: Re: [PATCH 0/24] make atomic_read() behave consistently across all architectures In-Reply-To: <20070816104250.GB2927@gondor.apana.org.au> References: <18115.52863.638655.658466@cargo.ozlabs.ibm.com> <20070816053945.GB32442@gondor.apana.org.au> <18115.62741.807704.969977@cargo.ozlabs.ibm.com> <20070816070907.GA964@gondor.apana.org.au> <46C40587.7050708@s5r6.in-berlin.de> <20070816081049.GA1431@gondor.apana.org.au> <46C41EE4.9090806@s5r6.in-berlin.de> <46C42767.4070104@s5r6.in-berlin.de> <20070816104250.GB2927@gondor.apana.org.au> X-Mailer: VM 7.19 under Emacs 21.4.1 Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 977 Lines: 23 Herbert Xu writes: > So the point here is that if you don't mind getting a stale > value from the CPU cache when doing an atomic_read, then > surely you won't mind getting a stale value from the compiler > "cache". No, that particular argument is bogus, because there is a cache coherency protocol operating to keep the CPU cache coherent with stores from other CPUs, but there isn't any such protocol (nor should there be) for a register used as a "cache". (Linux requires SMP systems to keep any CPU caches coherent as far as accesses by other CPUs are concerned. It doesn't support any SMP systems that are not cache-coherent as far as CPU accesses are concerned. It does support systems with non-cache-coherent DMA.) Paul. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/