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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB5278.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 01f66919-3ae3-499b-3787-08dae4949186 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Dec 2022 03:19:57.3819 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: e0jxZfoouLaTjWWv5vHRbi508vd/MB6CQMkLyOeG/KZx8FGN81hiK0BrM+4e/N2QZoB903auOXJ0BrioCi2gXw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8012 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [AMD Official Use Only - General] > -----Original Message----- > From: Huang, Ray > Sent: Friday, December 23, 2022 10:16 AM > To: Yuan, Perry > Cc: rafael.j.wysocki@intel.com; Limonciello, Mario > ; viresh.kumar@linaro.org; Sharma, Deepak > ; Fontenot, Nathan > ; Deucher, Alexander > ; Huang, Shimmer > ; Du, Xiaojian ; Meng, > Li (Jassmine) ; Karny, Wyes ; > linux-pm@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v8 01/13] ACPI: CPPC: Add AMD pstate energy > performance preference cppc control >=20 > On Mon, Dec 19, 2022 at 02:40:30PM +0800, Yuan, Perry wrote: > > From: Perry Yuan > > > > Add support for setting and querying EPP preferences to the generic > > CPPC driver. This enables downstream drivers such as amd-pstate to > > discover and use these values > > > > Downstream drivers that want to use the new symbols cppc_get_epp_caps > > and cppc_set_epp_perf for querying and setting EPP preferences will > > need to call cppc_set_epp_perf to enable the EPP function firstly. > > > > Signed-off-by: Perry Yuan > > --- > > drivers/acpi/cppc_acpi.c | 76 > > +++++++++++++++++++++++++++++++++++++--- > > include/acpi/cppc_acpi.h | 12 +++++++ > > 2 files changed, 83 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index > > 093675b1a1ff..81081eb899ea 100644 > > --- a/drivers/acpi/cppc_acpi.c > > +++ b/drivers/acpi/cppc_acpi.c > > @@ -1093,6 +1093,9 @@ static int cppc_get_perf(int cpunum, enum > > cppc_regs reg_idx, u64 *perf) { > > struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpunum); > > struct cpc_register_resource *reg; > > + int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpunum); > > + struct cppc_pcc_data *pcc_ss_data =3D NULL; > > + int ret =3D -EINVAL; > > > > if (!cpc_desc) { > > pr_debug("No CPC descriptor for CPU:%d\n", cpunum); @@ > -1102,10 > > +1105,6 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, > u64 *perf) > > reg =3D &cpc_desc->cpc_regs[reg_idx]; > > > > if (CPC_IN_PCC(reg)) { > > - int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpunum); > > - struct cppc_pcc_data *pcc_ss_data =3D NULL; > > - int ret =3D 0; > > - >=20 > Do you have any specific reason to move this piece out of if-condition? Move the declaration ahead of the If conditions like other functions did. It looks more reasonable and no functions impact.=20 Perry.=20 >=20 > > if (pcc_ss_id < 0) > > return -EIO; > > > > @@ -1125,7 +1124,7 @@ static int cppc_get_perf(int cpunum, enum > > cppc_regs reg_idx, u64 *perf) > > > > cpc_read(cpunum, reg, perf); > > > > - return 0; > > + return ret; > > } > > > > /** > > @@ -1153,6 +1152,19 @@ int cppc_get_nominal_perf(int cpunum, u64 > *nominal_perf) > > return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); } > > > > +/** > > + * cppc_get_epp_perf - Get the epp register value. > > + * @cpunum: CPU from which to get epp preference value. > > + * @epp_perf: Return address. > > + * > > + * Return: 0 for success, -EIO otherwise. > > + */ > > +int cppc_get_epp_perf(int cpunum, u64 *epp_perf) { > > + return cppc_get_perf(cpunum, ENERGY_PERF, epp_perf); } > > +EXPORT_SYMBOL_GPL(cppc_get_epp_perf); > > + >=20 > This function is enough to get the epp value. >=20 > Thanks, > Ray >=20 > > /** > > * cppc_get_perf_caps - Get a CPU's performance capabilities. > > * @cpunum: CPU from which to get capabilities info. > > @@ -1365,6 +1377,60 @@ int cppc_get_perf_ctrs(int cpunum, struct > > cppc_perf_fb_ctrs *perf_fb_ctrs) } > > EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); > > > > +/* > > + * Set Energy Performance Preference Register value through > > + * Performance Controls Interface > > + */ > > +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, > > +bool enable) { > > + int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpu); > > + struct cpc_register_resource *epp_set_reg; > > + struct cpc_register_resource *auto_sel_reg; > > + struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); > > + struct cppc_pcc_data *pcc_ss_data =3D NULL; > > + int ret =3D -EINVAL; > > + > > + if (!cpc_desc) { > > + pr_debug("No CPC descriptor for CPU:%d\n", cpu); > > + return -ENODEV; > > + } > > + > > + auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; > > + epp_set_reg =3D &cpc_desc->cpc_regs[ENERGY_PERF]; > > + > > + if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) { > > + if (pcc_ss_id < 0) { > > + pr_debug("Invalid pcc_ss_id\n"); > > + return -ENODEV; > > + } > > + > > + if (CPC_SUPPORTED(auto_sel_reg)) { > > + ret =3D cpc_write(cpu, auto_sel_reg, enable); > > + if (ret) > > + return ret; > > + } > > + > > + if (CPC_SUPPORTED(epp_set_reg)) { > > + ret =3D cpc_write(cpu, epp_set_reg, perf_ctrls- > >energy_perf); > > + if (ret) > > + return ret; > > + } > > + > > + pcc_ss_data =3D pcc_data[pcc_ss_id]; > > + > > + down_write(&pcc_ss_data->pcc_lock); > > + /* after writing CPC, transfer the ownership of PCC to > platform */ > > + ret =3D send_pcc_cmd(pcc_ss_id, CMD_WRITE); > > + up_write(&pcc_ss_data->pcc_lock); > > + } else { > > + ret =3D -ENOTSUPP; > > + pr_debug("_CPC in PCC is not supported\n"); > > + } > > + > > + return ret; > > +} > > +EXPORT_SYMBOL_GPL(cppc_set_epp_perf); > > + > > /** > > * cppc_set_enable - Set to enable CPPC on the processor by writing th= e > > * Continuous Performance Control package EnableRegister field. > > diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index > > c5614444031f..6b487a5bd638 100644 > > --- a/include/acpi/cppc_acpi.h > > +++ b/include/acpi/cppc_acpi.h > > @@ -108,12 +108,14 @@ struct cppc_perf_caps { > > u32 lowest_nonlinear_perf; > > u32 lowest_freq; > > u32 nominal_freq; > > + u32 energy_perf; > > }; > > > > struct cppc_perf_ctrls { > > u32 max_perf; > > u32 min_perf; > > u32 desired_perf; > > + u32 energy_perf; > > }; > > > > struct cppc_perf_fb_ctrs { > > @@ -149,6 +151,8 @@ extern bool cpc_ffh_supported(void); extern bool > > cpc_supported_by_cpu(void); extern int cpc_read_ffh(int cpunum, > > struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, > > struct cpc_reg *reg, u64 val); > > +extern int cppc_get_epp_perf(int cpunum, u64 *epp_perf); extern int > > +cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool > > +enable); > > #else /* !CONFIG_ACPI_CPPC_LIB */ > > static inline int cppc_get_desired_perf(int cpunum, u64 > > *desired_perf) { @@ -202,6 +206,14 @@ static inline int > > cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) { > > return -ENOTSUPP; > > } > > +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls > > +*perf_ctrls, bool enable) { > > + return -ENOTSUPP; > > +} > > +static inline int cppc_get_epp_perf(int cpunum, u64 *epp_perf) { > > + return -ENOTSUPP; > > +} > > #endif /* !CONFIG_ACPI_CPPC_LIB */ > > > > #endif /* _CPPC_ACPI_H*/ > > -- > > 2.34.1 > >