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Date:   Fri, 23 Dec 2022 11:39:57 +0100
From:   Johan Hovold <johan@kernel.org>
To:     Brian Masney <bmasney@redhat.com>
Cc:     andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        quic_shazhuss@quicinc.com, konrad.dybcio@linaro.org,
        robh+dt@kernel.org, johan+linaro@kernel.org,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, ahalaney@redhat.com,
        echanude@redhat.com
Subject: Re: [PATCH v3 5/7] arm64: dts: qcom: sc8280xp: add missing spi nodes
Message-ID: <Y6WFfSedn7hvEeAA@hovoldconsulting.com>
References: <20221220192854.521647-1-bmasney@redhat.com>
 <20221220192854.521647-6-bmasney@redhat.com>
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On Tue, Dec 20, 2022 at 02:28:52PM -0500, Brian Masney wrote:
> Add the missing nodes for the spi buses that's present on this SoC.
> 
> This work was derived from various patches that Qualcomm delivered
> to Red Hat in a downstream kernel.
> 
> Signed-off-by: Brian Masney <bmasney@redhat.com>
> ---
> Changes from v2 to v3
> - None
> 
> Changes from v1 to v2
> - Dropped qupX_ prefix from labels. (Johan)
> - Dropped spi-max-frequency property from spi nodes. (Shazad)
> 
>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 360 +++++++++++++++++++++++++
>  1 file changed, 360 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index a502d4e19d98..4591d411f5fb 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -829,6 +829,21 @@ i2c16: i2c@880000 {
>  				status = "disabled";
>  			};
>  
> +			spi16: spi@880000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0 0x00880000 0 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;

So please move this two after 'reg' as well.

> +				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
> +				                <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
> +				                <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
> +				interconnect-names = "qup-core", "qup-config", "qup-memory";

Shouldn't the spi version of these nodes also have a power-domain
property?

> +				status = "disabled";
> +			};

Johan