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From:   Mohan Kumar <mkumard@nvidia.com>
To:     <ldewangan@nvidia.com>, <jonathanh@nvidia.com>, <vkoul@kernel.org>,
        <thierry.reding@gmail.com>
CC:     <dmaengine@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <stable-commits@vger.kernel.org>,
        Mohan Kumar <mkumard@nvidia.com>
Subject: [PATCH] dmaengine: tegra210-adma: fix global intr clear
Date:   Mon, 26 Dec 2022 12:21:53 +0530
Message-ID: <20221226065153.5558-1-mkumard@nvidia.com>
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The current global interrupt clear programming register offset
was not correct. Fix the programming with right offset

fixes: 'commit ded1f3db4cd6
	("dmaengine: tegra210-adma: prepare for supporting newer Tegra chips")'

Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
---
 drivers/dma/tegra210-adma.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
index ae39b52012b2..487f8fb411b5 100644
--- a/drivers/dma/tegra210-adma.c
+++ b/drivers/dma/tegra210-adma.c
@@ -221,7 +221,9 @@ static int tegra_adma_init(struct tegra_adma *tdma)
 	int ret;
 
 	/* Clear any interrupts */
-	tdma_write(tdma, tdma->cdata->global_int_clear, 0x1);
+	tdma_write(tdma,
+		   tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear,
+		   0x1);
 
 	/* Assert soft reset */
 	tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
-- 
2.17.1