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Message-ID: <732352f3-fda0-039e-4fef-ceb6f5348086@gmail.com>
Date:   Tue, 27 Dec 2022 12:55:08 +0100
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Subject: Re: [PATCHv3 linux-next 3/4] ARM: dts: rockchip: rv1126: Add GMAC
 node
To:     Anand Moon <anand@edgeble.ai>, Heiko Stuebner <heiko@sntech.de>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Richard Cochran <richardcochran@gmail.com>
Cc:     Jagan Teki <jagan@edgeble.ai>,
        linux-arm-kernel@lists.infradead.org,
        linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, netdev@vger.kernel.org
References: <20221227104837.27208-1-anand@edgeble.ai>
 <20221227104837.27208-3-anand@edgeble.ai>
Content-Language: en-US
From:   Johan Jonker <jbx6244@gmail.com>
In-Reply-To: <20221227104837.27208-3-anand@edgeble.ai>
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On 12/27/22 11:48, Anand Moon wrote:
> Rockchip RV1126 has GMAC 10/100/1000M ethernet controller
> add GMAC node for RV1126 SoC.
> 
> Signed-off-by: Anand Moon <anand@edgeble.ai>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> v3: drop the gmac_clkin_m0 & gmac_clkin_m1 fix clock node which are not
> used, Add SoB of Jagan Teki.
> V2: drop SoB of Jagan Teki.
> ---
>  arch/arm/boot/dts/rv1126.dtsi | 49 +++++++++++++++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
> index 1cb43147e90b..e20fdd0d333c 100644
> --- a/arch/arm/boot/dts/rv1126.dtsi
> +++ b/arch/arm/boot/dts/rv1126.dtsi
> @@ -90,6 +90,55 @@ xin24m: oscillator {
>  		#clock-cells = <0>;
>  	};
>  

> +	gmac: ethernet@ffc40000 {

Nodes with a reg property are sort on reg address.
Heiko can fix that.. ;)

	timer0: timer@ff660000 {
	gmac: ethernet@ffc40000 {
	emmc: mmc@ffc50000 {

> +		compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
> +		reg = <0xffc40000 0x4000>;
> +		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "macirq", "eth_wake_irq";
> +		rockchip,grf = <&grf>;
> +		clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
> +			 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
> +			 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
> +			 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
> +		clock-names = "stmmaceth", "mac_clk_rx",
> +			      "mac_clk_tx", "clk_mac_ref",
> +			      "aclk_mac", "pclk_mac",
> +			      "clk_mac_speed", "ptp_ref";
> +		resets = <&cru SRST_GMAC_A>;
> +		reset-names = "stmmaceth";
> +
> +		snps,mixed-burst;
> +		snps,tso;
> +
> +		snps,axi-config = <&stmmac_axi_setup>;
> +		snps,mtl-rx-config = <&mtl_rx_setup>;
> +		snps,mtl-tx-config = <&mtl_tx_setup>;
> +		status = "disabled";
> +
> +		mdio: mdio {
> +			compatible = "snps,dwmac-mdio";
> +			#address-cells = <0x1>;
> +			#size-cells = <0x0>;
> +		};
> +
> +		stmmac_axi_setup: stmmac-axi-config {
> +			snps,wr_osr_lmt = <4>;
> +			snps,rd_osr_lmt = <8>;
> +			snps,blen = <0 0 0 0 16 8 4>;
> +		};
> +
> +		mtl_rx_setup: rx-queues-config {
> +			snps,rx-queues-to-use = <1>;
> +			queue0 {};
> +		};
> +
> +		mtl_tx_setup: tx-queues-config {
> +			snps,tx-queues-to-use = <1>;
> +			queue0 {};
> +		};
> +	};
> +
>  	grf: syscon@fe000000 {
>  		compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
>  		reg = <0xfe000000 0x20000>;