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[2620:137:e000::1:20]) by mx.google.com with ESMTP id hz3-20020a1709072ce300b007c18f5f64cfsi12220253ejc.996.2022.12.27.13.11.51; Tue, 27 Dec 2022 13:12:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=QbNG6ewT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231236AbiL0VJE (ORCPT + 66 others); Tue, 27 Dec 2022 16:09:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231716AbiL0VIO (ORCPT ); Tue, 27 Dec 2022 16:08:14 -0500 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DC2BDF51 for ; Tue, 27 Dec 2022 13:02:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672174924; x=1703710924; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zSTaTcLJbOegMxQuinD52HPOguvdV7463+YMjh/di6M=; b=QbNG6ewTHFunD2xBjnXNfzAZdhiwNF/NXhr6015exw+HUcLdDE2+aP7d OpdKI8mom8bR+rQh1lemFgNSc2nRqU5WsTHN1i51C4HqxV+VO81n7ZL40 oagILfvgWjjVtZnOddFJXDKNpRyM0cblWU055Llx84txBQU8ZBKBOuqCV URuZGEuk2wUdexKteWJsS2pfw8FmqwVanbRLiFMIBHlCATlIry5RqccMd Xp+SukN9Dwt7D48r1ht2zAj7rq8IeB5HZzMCa5rq7WnygXmbNQie6xHfJ BainoFy9e/5Q3Ns3KJyVAPqCAlIzTu0sUvlCJQxcq32njWBbS0YfNXAea g==; X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="304259681" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="304259681" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 13:02:03 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="760435295" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="760435295" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 13:02:01 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v3 1/2] x86/microcode: Add a parameter to microcode_check() to store CPU capabilities Date: Tue, 27 Dec 2022 13:01:43 -0800 Message-Id: <20221227210144.5112-1-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is a preparation before the next patch uses this to compare CPU capabilities after performing an update. Add a parameter to store CPU capabilities before performing a microcode update. Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- arch/x86/include/asm/processor.h | 2 +- arch/x86/kernel/cpu/common.c | 12 +++++------- arch/x86/kernel/cpu/microcode/core.c | 3 ++- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 4e35c66edeb7..387578049de0 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -697,7 +697,7 @@ bool xen_set_default_idle(void); #endif void __noreturn stop_this_cpu(void *dummy); -void microcode_check(void); +void microcode_check(struct cpuinfo_x86 *info); enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9cfca3d7d0e2..b9c7529c920e 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2302,25 +2302,23 @@ void cpu_init_secondary(void) * only when microcode has been updated. Caller holds microcode_mutex and CPU * hotplug lock. */ -void microcode_check(void) +void microcode_check(struct cpuinfo_x86 *info) { - struct cpuinfo_x86 info; - perf_check_microcode(); /* Reload CPUID max function as it might've changed. */ - info.cpuid_level = cpuid_eax(0); + info->cpuid_level = cpuid_eax(0); /* * Copy all capability leafs to pick up the synthetic ones so that * memcmp() below doesn't fail on that. The ones coming from CPUID will * get overwritten in get_cpu_cap(). */ - memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); + memcpy(&info->x86_capability, &boot_cpu_data.x86_capability, sizeof(info->x86_capability)); - get_cpu_cap(&info); + get_cpu_cap(info); - if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) + if (!memcmp(&info->x86_capability, &boot_cpu_data.x86_capability, sizeof(info->x86_capability))) return; pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index c4cd7328177b..d86a4f910a6b 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -439,6 +439,7 @@ static int __reload_late(void *info) static int microcode_reload_late(void) { int old = boot_cpu_data.microcode, ret; + struct cpuinfo_x86 info; pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); @@ -448,7 +449,7 @@ static int microcode_reload_late(void) ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret == 0) - microcode_check(); + microcode_check(&info); pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); -- 2.34.1