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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Wed, 28 Dec 2022 23:36:26 +0000
Message-ID: <CA+V-a8sFV+vqXN8mA4c8wKe15chcZKsiZf1gCdcc+ZoFWtNGtw@mail.gmail.com>
Subject: Re: [PATCH v2 9/9] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY
 interrupt support for ETH{0/1}
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Geert,

Thank you for the review.

On Tue, Dec 27, 2022 at 1:02 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Dec 21, 2022 at 1:04 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
> > ETH1 respectively.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> > @@ -6,6 +6,7 @@
> >   */
> >
> >  #include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
> >  #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> >
> >  / {
> > @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 {
> >                 compatible = "ethernet-phy-id0022.1640",
> >                              "ethernet-phy-ieee802.3-c22";
> >                 reg = <7>;
> > +               interrupt-parent = <&irqc>;
>
> Note that arch/riscv/boot/dts/renesas/r9a07g043f.dtsi does not have
> the irqc node yet, so I cannot take this as-is.
>
Agreed, is it OK if we temporarily add the (above+below) properties in
the boards DTS and once we have full fledged support for RZ/Five we
move it back to the SoM DTSi (as done in this patch)?

Cheers,
Prabhakar

> > +               interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
> >                 rxc-skew-psec = <2400>;
> >                 txc-skew-psec = <2400>;
> >                 rxdv-skew-psec = <0>;
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds