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Thu, 29 Dec 2022 21:19:31 -0800 (PST) MIME-Version: 1.0 References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> <20221223094259.87373-8-angelogioacchino.delregno@collabora.com> In-Reply-To: <20221223094259.87373-8-angelogioacchino.delregno@collabora.com> From: Chen-Yu Tsai Date: Fri, 30 Dec 2022 13:19:21 +0800 Message-ID: Subject: Re: [PATCH v2 07/23] clk: mediatek: clk-mtk: Add dummy clock ops To: AngeloGioacchino Del Regno Cc: mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 23, 2022 at 5:43 PM AngeloGioacchino Del Regno wrote: > > In order to migrate some (few) old clock drivers to the common > mtk_clk_simple_probe() function, add dummy clock ops to be able > to insert a dummy clock with ID 0 at the beginning of the list. > > Signed-off-by: AngeloGioacchino Del Regno > --- > drivers/clk/mediatek/clk-mtk.c | 15 +++++++++++++++ > drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++ > 2 files changed, 34 insertions(+) > > diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c > index a1ab34305b95..d05364e17e95 100644 > --- a/drivers/clk/mediatek/clk-mtk.c > +++ b/drivers/clk/mediatek/clk-mtk.c > @@ -18,6 +18,21 @@ > #include "clk-mtk.h" > #include "clk-gate.h" > > +const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; You could probably just use an empty { }, since the contents don't matter. It would make any possible future changes to |struct mtk_gate_regs| touch one less place. Otherwise, Reviewed-by: Chen-Yu Tsai > + > +static int mtk_clk_dummy_enable(struct clk_hw *hw) > +{ > + return 0; > +} > + > +static void mtk_clk_dummy_disable(struct clk_hw *hw) { } > + > +const struct clk_ops mtk_clk_dummy_ops = { > + .enable = mtk_clk_dummy_enable, > + .disable = mtk_clk_dummy_disable, > +}; > +EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops); > + > static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data, > unsigned int clk_num) > { > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h > index 15122504c02d..dd43235285db 100644 > --- a/drivers/clk/mediatek/clk-mtk.h > +++ b/drivers/clk/mediatek/clk-mtk.h > @@ -22,6 +22,25 @@ > > struct platform_device; > > +/* > + * We need the clock IDs to start from zero but to maintain devicetree > + * backwards compatibility we can't change bindings to start from zero. > + * Only a few platforms are affected, so we solve issues given by the > + * commonized MTK clocks probe function(s) by adding a dummy clock at > + * the beginning where needed. > + */ > +#define CLK_DUMMY 0 > + > +extern const struct clk_ops mtk_clk_dummy_ops; > +extern const struct mtk_gate_regs cg_regs_dummy; > + > +#define GATE_DUMMY(_id, _name) { \ > + .id = _id, \ > + .name = _name, \ > + .regs = &cg_regs_dummy, \ > + .ops = &mtk_clk_dummy_ops, \ > + } > + > struct mtk_fixed_clk { > int id; > const char *name; > -- > 2.39.0 >