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References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> <20221230061309.16643-1-miles.chen@mediatek.com>
In-Reply-To: <20221230061309.16643-1-miles.chen@mediatek.com>
From:   Chen-Yu Tsai <wenst@chromium.org>
Date:   Fri, 30 Dec 2022 14:42:39 +0800
Message-ID: <CAGXv+5HqLc2xsz6b_d5hrPiAu363aMcJkQrqX32ukA2pcsj6kQ@mail.gmail.com>
Subject: Re: [PATCH v2 00/23] MediaTek clocks cleanups and improvements
To:     Miles Chen <miles.chen@mediatek.com>
Cc:     angelogioacchino.delregno@collabora.com,
        chun-jie.chen@mediatek.com, daniel@makrotopia.org,
        devicetree@vger.kernel.org, fparent@baylibre.com,
        ikjn@chromium.org, johnson.wang@mediatek.com,
        jose.exposito89@gmail.com, kernel@collabora.com,
        krzysztof.kozlowski+dt@linaro.org,
        linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
        matthias.bgg@gmail.com, msp@baylibre.com, mturquette@baylibre.com,
        nfraprado@collabora.com, pablo.sun@mediatek.com,
        rex-bc.chen@mediatek.com, robh+dt@kernel.org, ryder.lee@kernel.org,
        sam.shih@mediatek.com, sboyd@kernel.org, weiyi.lu@mediatek.com,
        y.oudjana@protonmail.com, yangyingliang@huawei.com
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On Fri, Dec 30, 2022 at 2:13 PM Miles Chen <miles.chen@mediatek.com> wrote:
> > Changes in v2:
> >  - Moved dt-bindings CLK_DUMMY to clk-mtk.h instead
> >
> >
> > This series performs cleanups and improvements on MediaTek clock
> > drivers, greatly reducing code duplication (hence also reducing
> > kernel size).
> >
> > There would be a lot to say about it, but summarizing:
> >
> > * Propagates struct device where possible in order to introduce the
> >   possibility of using Runtime PM on clock drivers as needed,
> >   possibly enhancing reliability of some platforms (obviously, this
> >   will do nothing unless power-domains are added to devicetree);
> >
> > * Cleans up some duplicated clock(s) registration attempt(s): on
> >   some platforms the 26M fixed factor clock is registered early,
> >   but then upon platform_driver probe, an attempt to re-register
> >   that clock was performed;
> >
> > * Removes some early clock registration where possible, moving
> >   everything to platform_driver clock probe;
> >
> > * Breaks down the big MT8173 clock driver in multiple ones, as it's
> >   already done with the others, cleans it up and adds possibility
> >   possibility to compile non-boot-critical clock drivers (for 8173)
> >   as modules;
> >
> > * Extends the common mtk_clk_simple_probe() function to be able to
> >   register multiple MediaTek clock types;
> >
> > * Removes duplicated [...]_probe functions from multiple MediaTek SoC
> >   clock drivers, migrating almost everything to the common functions
> >   mtk_clk_simple_probe();
> >
> > * Adds a .remove() callback, pointing to the common mtk_clk_simple_remove()
> >   function to all clock drivers that were migrated to the common probe;
> >
> > * Some more spare cleanups here and there.
> >
> > All of this was manually tested on various Chromebooks (with different MTK
> > SoCs) and no regression was detected.
> >
> > Cheers!
>
> I tested this v2 series on mt6779 and mt8192 without any problem.

Please give Tested-by. :)