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Fri, 30 Dec 2022 00:10:10 -0800 (PST) MIME-Version: 1.0 References: <20221223094259.87373-16-angelogioacchino.delregno@collabora.com> <20221228083123.15298-1-miles.chen@mediatek.com> In-Reply-To: <20221228083123.15298-1-miles.chen@mediatek.com> From: Chen-Yu Tsai Date: Fri, 30 Dec 2022 16:09:59 +0800 Message-ID: Subject: Re: [PATCH v2 15/23] clk: mediatek: mt8192: Join top_adj_divs and top_muxes To: Miles Chen Cc: angelogioacchino.delregno@collabora.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, devicetree@vger.kernel.org, fparent@baylibre.com, ikjn@chromium.org, johnson.wang@mediatek.com, jose.exposito89@gmail.com, kernel@collabora.com, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, msp@baylibre.com, mturquette@baylibre.com, nfraprado@collabora.com, pablo.sun@mediatek.com, rex-bc.chen@mediatek.com, robh+dt@kernel.org, ryder.lee@kernel.org, sam.shih@mediatek.com, sboyd@kernel.org, weiyi.lu@mediatek.com, y.oudjana@protonmail.com, yangyingliang@huawei.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 28, 2022 at 4:31 PM Miles Chen wrote: > > Hi, > > > These two are both mtk_composite arrays, one dependent on another, but > > that's something that the clock framework is supposed to sort out and > > anyway registering them separately isn't going to ease the framework's > > job in checking dependencies. > > > > Put the contents of top_adj_divs in top_muxes to join them together > > and register them in one shot. > > > > In mt8192, we can join top_adj_divs and top_muxes: > > mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt8192_clk_lock, > top_clk_data); > mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8192_clk_lock, > top_clk_data); > > However, there are other top_adj_divs[] and top_muxes[] in different types so > we cannot join them. > > For example: > in drivers/clk/mediatek/clk-mt8167.c:mtk_topckgen_init(): > > mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, > &mt8167_clk_lock, clk_data); > mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), > base, &mt8167_clk_lock, clk_data); > > So we can join top_adj_divs and top_muxes in some platforms, but we > cannot join top_adj_divs and top_muxes in some other platforms. > > I'm afraid that this will confuses people. I think the confusion comes from the macro names. It's not exactly clear that DIV_GATE is for composite clocks, while DIV_ADJ is for divider clocks. Doubly so for the mux related types. Either way, using the wrong macro or the wrong type will cause the compiler to complain, so I think it's something we can live with. If it's still not working out, maybe we should rethink the naming. ChenYu