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From:   Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
To:     <swboyd@chromium.org>, <agross@kernel.org>, <andersson@kernel.org>,
        <robh+dt@kernel.org>, <broonie@kernel.org>,
        <quic_plai@quicinc.com>, <krzysztof.kozlowski+dt@linaro.org>,
        <konrad.dybcio@somainline.org>, <mturquette@baylibre.com>,
        <sboyd@kernel.org>, <linux-arm-msm@vger.kernel.org>,
        <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <quic_rohkumar@quicinc.com>
CC:     Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Subject: [PATCH v2 3/4] clk: qcom: lpasscc-sc7280: Remove qdsp6ss clock control
Date:   Fri, 30 Dec 2022 19:13:18 +0530
Message-ID: <1672407799-13768-4-git-send-email-quic_srivasam@quicinc.com>
In-Reply-To: <1672407799-13768-1-git-send-email-quic_srivasam@quicinc.com>
References: <1672407799-13768-1-git-send-email-quic_srivasam@quicinc.com>
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The qdsp6ss memory region is being shared by ADSP remoteproc device and
lpasscc clock device, hence causing memory conflict.
As the qdsp6ss clocks are being enabled in remoteproc driver,
remove clock controlling in the clock driver.

Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280")

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
 drivers/clk/qcom/lpasscc-sc7280.c | 63 +--------------------------------------
 1 file changed, 1 insertion(+), 62 deletions(-)

diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
index 5c1e17b..87e1c21 100644
--- a/drivers/clk/qcom/lpasscc-sc7280.c
+++ b/drivers/clk/qcom/lpasscc-sc7280.c
@@ -30,48 +30,6 @@ static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
 	},
 };
 
-static struct clk_branch lpass_qdsp6ss_core_clk = {
-	.halt_reg = 0x20,
-	/* CLK_OFF would not toggle until LPASS is out of reset */
-	.halt_check = BRANCH_HALT_SKIP,
-	.clkr = {
-		.enable_reg = 0x20,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "lpass_qdsp6ss_core_clk",
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
-static struct clk_branch lpass_qdsp6ss_xo_clk = {
-	.halt_reg = 0x38,
-	/* CLK_OFF would not toggle until LPASS is out of reset */
-	.halt_check = BRANCH_HALT_SKIP,
-	.clkr = {
-		.enable_reg = 0x38,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "lpass_qdsp6ss_xo_clk",
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
-static struct clk_branch lpass_qdsp6ss_sleep_clk = {
-	.halt_reg = 0x3c,
-	/* CLK_OFF would not toggle until LPASS is out of reset */
-	.halt_check = BRANCH_HALT_SKIP,
-	.clkr = {
-		.enable_reg = 0x3c,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "lpass_qdsp6ss_sleep_clk",
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
 static struct regmap_config lpass_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
@@ -90,18 +48,6 @@ static const struct qcom_cc_desc lpass_cc_top_sc7280_desc = {
 	.num_clks = ARRAY_SIZE(lpass_cc_top_sc7280_clocks),
 };
 
-static struct clk_regmap *lpass_qdsp6ss_sc7280_clocks[] = {
-	[LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
-	[LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
-	[LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
-};
-
-static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
-	.config = &lpass_regmap_config,
-	.clks = lpass_qdsp6ss_sc7280_clocks,
-	.num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
-};
-
 static int lpass_cc_sc7280_probe(struct platform_device *pdev)
 {
 	const struct qcom_cc_desc *desc;
@@ -118,17 +64,10 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
 		goto destroy_pm_clk;
 	}
 
-	lpass_regmap_config.name = "qdsp6ss";
-	desc = &lpass_qdsp6ss_sc7280_desc;
-
-	ret = qcom_cc_probe_by_index(pdev, 0, desc);
-	if (ret)
-		goto destroy_pm_clk;
-
 	lpass_regmap_config.name = "top_cc";
 	desc = &lpass_cc_top_sc7280_desc;
 
-	ret = qcom_cc_probe_by_index(pdev, 1, desc);
+	ret = qcom_cc_probe_by_index(pdev, 0, desc);
 	if (ret)
 		goto destroy_pm_clk;
 
-- 
2.7.4