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Date:   Sat, 31 Dec 2022 01:12:04 +0300
From:   Sergey Matyukevich <geomatsi@gmail.com>
To:     Icenowy Zheng <uwu@icenowy.me>
Cc:     Guo Ren <guoren@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Heiko Stuebner <heiko@sntech.de>,
        Nathan Chancellor <nathan@kernel.org>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding
Message-ID: <Y69iNMQ60gXYkKus@curiosity>
References: <20221227020258.303900-1-uwu@icenowy.me>
 <CAJF2gTSGvEnTqEqR9f+zU8T3VS8FoCtsgSk=9hz6cWxAL630zQ@mail.gmail.com>
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> > The dcache.cva encoding shown in the comments are wrong, it's for
> > dcache.cval1 (which is restricted to L1) instead.
> >
> > Fix this in the comment and in the hardcoded instruction.
> >
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > ---
> > The code is tested on a LiteX SoC with OpenC906 core, and it
> > successfully boots to Systemd on a SD card connected to LiteSDCard.
> >
> > This change should be not noticable on C906, but on multi-core C910
> > cluster it should fixes something. Unfortunately TH1520 seems to be not
> > so ready to test mainline patches on.
> >
> >  arch/riscv/include/asm/errata_list.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index 4180312d2a70..605800bd390e 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE(                                           \
> >   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> >   *   0000001    01001      rs1       000      00000  0001011
> >   * dcache.cva rs1 (clean, virtual address)
> > - *   0000001    00100      rs1       000      00000  0001011
> > + *   0000001    00101      rs1       000      00000  0001011
> >   *
> >   * dcache.cipa rs1 (clean then invalidate, physical address)
> >   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE(                                           \
> >   *   0000000    11001     00000      000      00000  0001011
> >   */
> >  #define THEAD_inval_A0 ".long 0x0265000b"
> > -#define THEAD_clean_A0 ".long 0x0245000b"
> > +#define THEAD_clean_A0 ".long 0x0255000b"
> >  #define THEAD_flush_A0 ".long 0x0275000b"
> >  #define THEAD_SYNC_S   ".long 0x0190000b"

Nice catch ! I experimented with T-Head RVB-ICE board on the up-to-date
upstream kernel, using device tree and some other bits from the vendor
kernel [1]. Without this patch, emmc on this board does not work since
noncoherent dma sync operations use incorrect 'clean' instruction.
Applying this patch fixes emmc operations, so

Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>

[1] https://github.com/T-head-Semi/linux/tree/linux-5.10.4

Regards,
Sergey