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Message-ID: <5818a83e644eb9c868d4cf65117983e08ba1c17f.camel@icenowy.me>
Subject: Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding
From:   Icenowy Zheng <uwu@icenowy.me>
To:     Sergey Matyukevich <geomatsi@gmail.com>
Cc:     Guo Ren <guoren@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Heiko Stuebner <heiko@sntech.de>,
        Nathan Chancellor <nathan@kernel.org>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Date:   Sat, 31 Dec 2022 12:36:04 +0800
In-Reply-To: <Y69iNMQ60gXYkKus@curiosity>
References: <20221227020258.303900-1-uwu@icenowy.me>
         <CAJF2gTSGvEnTqEqR9f+zU8T3VS8FoCtsgSk=9hz6cWxAL630zQ@mail.gmail.com>
         <Y69iNMQ60gXYkKus@curiosity>
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=E5=9C=A8 2022-12-31=E6=98=9F=E6=9C=9F=E5=85=AD=E7=9A=84 01:12 +0300=EF=BC=
=8CSergey Matyukevich=E5=86=99=E9=81=93=EF=BC=9A
> > > The dcache.cva encoding shown in the comments are wrong, it's for
> > > dcache.cval1 (which is restricted to L1) instead.
> > >=20
> > > Fix this in the comment and in the hardcoded instruction.
> > >=20
> > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > > ---
> > > The code is tested on a LiteX SoC with OpenC906 core, and it
> > > successfully boots to Systemd on a SD card connected to
> > > LiteSDCard.
> > >=20
> > > This change should be not noticable on C906, but on multi-core
> > > C910
> > > cluster it should fixes something. Unfortunately TH1520 seems to
> > > be not
> > > so ready to test mainline patches on.
> > >=20
> > > =C2=A0arch/riscv/include/asm/errata_list.h | 4 ++--
> > > =C2=A01 file changed, 2 insertions(+), 2 deletions(-)
> > >=20
> > > diff --git a/arch/riscv/include/asm/errata_list.h
> > > b/arch/riscv/include/asm/errata_list.h
> > > index 4180312d2a70..605800bd390e 100644
> > > --- a/arch/riscv/include/asm/errata_list.h
> > > +++ b/arch/riscv/include/asm/errata_list.h
> > > @@ -102,7 +102,7 @@ asm
> > > volatile(ALTERNATIVE(=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \
> > > =C2=A0 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > > =C2=A0 *=C2=A0=C2=A0 0000001=C2=A0=C2=A0=C2=A0 01001=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 rs1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 000=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 00000=C2=A0 0001011
> > > =C2=A0 * dcache.cva rs1 (clean, virtual address)
> > > - *=C2=A0=C2=A0 0000001=C2=A0=C2=A0=C2=A0 00100=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 rs1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 000=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 00000=C2=A0 0001011
> > > + *=C2=A0=C2=A0 0000001=C2=A0=C2=A0=C2=A0 00101=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 rs1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 000=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 00000=C2=A0 0001011
> > > =C2=A0 *
> > > =C2=A0 * dcache.cipa rs1 (clean then invalidate, physical address)
> > > =C2=A0 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > > @@ -115,7 +115,7 @@ asm
> > > volatile(ALTERNATIVE(=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \
> > > =C2=A0 *=C2=A0=C2=A0 0000000=C2=A0=C2=A0=C2=A0 11001=C2=A0=C2=A0=C2=
=A0=C2=A0 00000=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 000=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 00000=C2=A0 0001011
> > > =C2=A0 */
> > > =C2=A0#define THEAD_inval_A0 ".long 0x0265000b"
> > > -#define THEAD_clean_A0 ".long 0x0245000b"
> > > +#define THEAD_clean_A0 ".long 0x0255000b"
> > > =C2=A0#define THEAD_flush_A0 ".long 0x0275000b"
> > > =C2=A0#define THEAD_SYNC_S=C2=A0=C2=A0 ".long 0x0190000b"
>=20
> Nice catch ! I experimented with T-Head RVB-ICE board on the up-to-
> date
> upstream kernel, using device tree and some other bits from the
> vendor
> kernel [1]. Without this patch, emmc on this board does not work
> since
> noncoherent dma sync operations use incorrect 'clean' instruction.
> Applying this patch fixes emmc operations, so

Thanks for testing on C910! I don't think this patch will make a
significant difference on C906, so it's valuable!

>=20
> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
>=20
> [1] https://github.com/T-head-Semi/linux/tree/linux-5.10.4
>=20
> Regards,
> Sergey