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Received: from DU2PR04MB8536.eurprd04.prod.outlook.com (2603:10a6:10:2d7::10) by AM7PR04MB6791.eurprd04.prod.outlook.com (2603:10a6:20b:103::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5944.19; Mon, 2 Jan 2023 15:29:23 +0000 Received: from DU2PR04MB8536.eurprd04.prod.outlook.com ([fe80::9ebd:cd48:9396:76f6]) by DU2PR04MB8536.eurprd04.prod.outlook.com ([fe80::9ebd:cd48:9396:76f6%6]) with mapi id 15.20.5944.019; Mon, 2 Jan 2023 15:29:23 +0000 Message-ID: <09bd4e26-3e1e-061f-e228-a06ac2e4ab90@theobroma-systems.com> Date: Mon, 2 Jan 2023 16:29:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH] clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent Content-Language: en-US To: Quentin Schulz , Stephen Boyd , Heiko Stuebner , Xing Zheng , Michael Turquette Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, stable@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org References: <20221117-rk3399-cifout-set-rate-parent-v1-0-432548d04081@theobroma-systems.com> From: Quentin Schulz In-Reply-To: <20221117-rk3399-cifout-set-rate-parent-v1-0-432548d04081@theobroma-systems.com> Content-Type: text/plain; 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Cheers, Quentin On 11/17/22 13:04, Quentin Schulz wrote: > From: Quentin Schulz > > clk_cifout is derived from clk_cifout_src through an integer divider > limited to 32. clk_cifout_src is a child of either cpll, gpll or npll > without any possibility of a divider of any sort. The default clock > parent is cpll. > > Let's allow clk_cifout to ask its parent clk_cifout_src to reparent in > order to find the real closest possible rate for clk_cifout and not one > derived from cpll only. > > Cc: stable@vger.kernel.org # 4.10+ > Fixes: fd8bc829336a ("clk: rockchip: fix the rk3399 cifout clock") > Signed-off-by: Quentin Schulz > --- > clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent > > This used to be correct before v4.10 but commit fd8bc829336a ("clk: rockchip: > fix the rk3399 cifout clock") incorrectly removed this ability while reworking > it. > > Note: this has been tested on top of v6.0.2 only but no changes were made to > this driver since. As for older stable releases, the git context seems identical > and there does not seem to have been any logical change introduced since v4.10 > so it should be pretty safe to apply. > > To: Michael Turquette > To: Stephen Boyd > To: Heiko Stuebner > To: Xing Zheng > Cc: linux-clk@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-rockchip@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > --- > drivers/clk/rockchip/clk-rk3399.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c > index 306910a3a0d38..9ebd6c451b3db 100644 > --- a/drivers/clk/rockchip/clk-rk3399.c > +++ b/drivers/clk/rockchip/clk-rk3399.c > @@ -1263,7 +1263,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { > RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, > RK3399_CLKGATE_CON(10), 7, GFLAGS), > > - COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0, > + COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT, > RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS), > > /* gic */ > > --- > base-commit: cc675d22e422442f6d230654a55a5fc5682ea018 > change-id: 20221117-rk3399-cifout-set-rate-parent-1fbf0173ef2d > > Best regards,