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From:   Samuel Holland <samuel@sholland.org>
To:     Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
        Robin Murphy <robin.murphy@arm.com>,
        Chen-Yu Tsai <wens@csie.org>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Rob Herring <robh+dt@kernel.org>
Cc:     iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
        linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, Maxime Ripard <mripard@kernel.org>,
        Samuel Holland <samuel@sholland.org>
Subject: [PATCH v2 0/6] iommu/sun50i: Allwinner D1 support
Date:   Mon,  2 Jan 2023 19:08:57 -0600
Message-Id: <20230103010903.11181-1-samuel@sholland.org>
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D1 is a RISC-V SoC from Allwinner's sunxi family. This series adds IOMMU
binding and driver support. The RISC-V architecture code still needs
some small updates to use an IOMMU for DMA[1][2]. I will send those
separately.

[1]: https://lore.kernel.org/linux-riscv/20220428010401.11323-1-samuel@sholland.org/
[2]: https://lore.kernel.org/linux-riscv/7b09e989-0aa1-a557-485e-572f69caf881@arm.com/

Changes in v2:
 - Disallow the 'resets' property for the D1 variant
 - Set bypass based on attached devices instead of using a fixed value

Samuel Holland (6):
  dt-bindings: iommu: sun50i: Add compatible for Allwinner D1
  iommu/sun50i: Track masters attached to the domain
  iommu/sun50i: Keep the bypass register up to date
  iommu/sun50i: Support variants without an external reset
  iommu/sun50i: Add support for the D1 variant
  riscv: dts: allwinner: d1: Add the IOMMU node

 .../iommu/allwinner,sun50i-h6-iommu.yaml      | 20 +++++-
 .../boot/dts/allwinner/sunxi-d1s-t113.dtsi    | 10 +++
 drivers/iommu/sun50i-iommu.c                  | 68 ++++++++++++++-----
 3 files changed, 79 insertions(+), 19 deletions(-)

-- 
2.37.4