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References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com>
In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com>
From:   Chen-Yu Tsai <wenst@chromium.org>
Date:   Tue, 3 Jan 2023 17:36:21 +0800
Message-ID: <CAGXv+5GekZUSe34DxiKzdnPr-GDsmJBfAgkS1RjrN-xdeXMN6g@mail.gmail.com>
Subject: Re: [PATCH v2 00/23] MediaTek clocks cleanups and improvements
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
Cc:     mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        johnson.wang@mediatek.com, miles.chen@mediatek.com,
        fparent@baylibre.com, chun-jie.chen@mediatek.com,
        sam.shih@mediatek.com, y.oudjana@protonmail.com,
        nfraprado@collabora.com, rex-bc.chen@mediatek.com,
        ryder.lee@kernel.org, daniel@makrotopia.org,
        jose.exposito89@gmail.com, yangyingliang@huawei.com,
        pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com,
        ikjn@chromium.org, linux-kernel@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
        kernel@collabora.com
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On Fri, Dec 23, 2022 at 5:43 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
>
> Changes in v2:
>  - Moved dt-bindings CLK_DUMMY to clk-mtk.h instead
>
>
> This series performs cleanups and improvements on MediaTek clock
> drivers, greatly reducing code duplication (hence also reducing
> kernel size).
>
> There would be a lot to say about it, but summarizing:
>
> * Propagates struct device where possible in order to introduce the
>   possibility of using Runtime PM on clock drivers as needed,
>   possibly enhancing reliability of some platforms (obviously, this
>   will do nothing unless power-domains are added to devicetree);
>
> * Cleans up some duplicated clock(s) registration attempt(s): on
>   some platforms the 26M fixed factor clock is registered early,
>   but then upon platform_driver probe, an attempt to re-register
>   that clock was performed;
>
> * Removes some early clock registration where possible, moving
>   everything to platform_driver clock probe;
>
> * Breaks down the big MT8173 clock driver in multiple ones, as it's
>   already done with the others, cleans it up and adds possibility
>   possibility to compile non-boot-critical clock drivers (for 8173)
>   as modules;
>
> * Extends the common mtk_clk_simple_probe() function to be able to
>   register multiple MediaTek clock types;
>
> * Removes duplicated [...]_probe functions from multiple MediaTek SoC
>   clock drivers, migrating almost everything to the common functions
>   mtk_clk_simple_probe();
>
> * Adds a .remove() callback, pointing to the common mtk_clk_simple_remove()
>   function to all clock drivers that were migrated to the common probe;
>
> * Some more spare cleanups here and there.
>
> All of this was manually tested on various Chromebooks (with different MTK
> SoCs) and no regression was detected.
>
> Cheers!
>
> AngeloGioacchino Del Regno (23):
>   clk: mediatek: mt8192: Correctly unregister and free clocks on failure
>   clk: mediatek: mt8192: Propagate struct device for gate clocks
>   clk: mediatek: clk-gate: Propagate struct device with
>     mtk_clk_register_gates()
>   clk: mediatek: cpumux: Propagate struct device where possible
>   clk: mediatek: clk-mtk: Propagate struct device for composites
>   clk: mediatek: clk-mux: Propagate struct device for mtk-mux
>   clk: mediatek: clk-mtk: Add dummy clock ops
>   clk: mediatek: mt8173: Migrate to platform driver and common probe
>   clk: mediatek: mt8173: Remove mtk_clk_enable_critical()
>   clk: mediatek: mt8173: Break down clock drivers and allow module build
>   clk: mediatek: Switch to mtk_clk_simple_probe() where possible
>   clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe()
>   clk: mediatek: mt8173: Migrate pericfg/topckgen to
>     mtk_clk_simple_probe()
>   clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs
>   clk: mediatek: mt8192: Join top_adj_divs and top_muxes
>   clk: mediatek: mt8186: Join top_adj_div and top_muxes
>   clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs
>   clk: mediatek: clk-mtk: Register MFG notifier in
>     mtk_clk_simple_probe()
>   clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe()
>   clk: mediatek: clk-mt8186-topckgen: Migrate to mtk_clk_simple_probe()
>   clk: mediatek: clk-mt6795-topckgen: Migrate to mtk_clk_simple_probe()
>   clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled
>   clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe()

Boot tested on MT8183 and MT8192 (which needs CLK_OPS_PARENT_ENABLE fix
I just sent), so for the whole series:

Tested-by: Chen-Yu Tsai <wenst@chromium.org>