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Subject: Re: RFC on drivers/memory vs drivers/edac memory mapping for DDR Controller
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Date:   Tue, 3 Jan 2023 15:12:45 +0200
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To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
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From:   "Shenhar, Talel" <talel@amazon.com>
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On 1/2/2023 6:25 PM, Krzysztof Kozlowski wrote:
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>
>
> On 02/01/2023 17:21, Shenhar, Talel wrote:
>> On 1/2/2023 3:59 PM, Krzysztof Kozlowski wrote:
>>> On 02/01/2023 14:44, Shenhar, Talel wrote:
>>>> On 1/2/2023 2:47 PM, Krzysztof Kozlowski wrote:
>>>>> On 02/01/2023 13:17, Shenhar, Talel wrote:
>>>>>
>>>>>> Things we had in mind:
>>>>>> 1) map more specific region to avoid conflict (we don't need the same
>>>>>> registers on both entity so if we do very specific multiple mapping this
>>>>>> shall be resolved)
>>>>>> 2) use other kernel API for mapping that doesn't do request_mem_region
>>>>>> (or use the reserve only for one of them)
>>>>>> 3) have single driver (edac mc) handle also the refresh rate
>>>>>> 4) export edac_mc.h and have the drivers/memory have all the needed code
>>>>>> to do both edac and refresh rate under drivers/memory
>>>>> None of these address the core problem - possibly inaccurate hardware
>>>>> description...
>>>> Can you elaborate on this inaccurate hardware description?
>>> I explained - using same IO address suggests you used Linux driver
>>> structure in your hardware description. I assume we talk here about
>>> Devicetree. If not, that's quite different case... then I guess ACPI,
>>> which I do not care - I am not it's maintainer.
>>>
>>>> Also, I'd like to write down my understanding of your response from above:
>>>>
>>>> it seems you see as possible solution both using different API that
>>>> allow overlapping (solution 2) and also for splitting the IO address
>>>> space to finer pieces to achieve full HW description (solution 1)
>>> No. Sorry, we probably talk about two different things.
>>>
>>> You started writing that you have a hardware described as one IO address
>>> space and now have a problem developing drivers for it.
>>>
>>> The driver model for this is entirely different problem than problem of
>>> accurate hardware description. Whether you described HW correct or not,
>>> I don't know. You did not provide any details here, like DTS or bindings
>>> (if we talk about Devicetree).
>>>
>>> Having multiple drivers using similar resources is already solved many
>>> times (MFD, syscon).
>>>
>>> Whether the solution is correct or not is one more (third) topic: poking
>>> to same IO address space from two different drivers is error-prone. This
>>> one is solvable with splitting IO address space.
>>>
>>> Best regards,
>>> Krzysztof
>>
>> You are right.
>>
>> Let me elaborate on this.
>>
>> We will write down the hardware description via device tree.
>>
>> Then we will write the driver which will honor that binding.
>>
>> So the question is what is the best practice there assuming there is no
>> shared registers however there is overlapping.
> The correct solution is to describe hardware. The hardware is memory
> controller. There is no hardware called "scaller of memory controller".
> There is no hardware called "EDAC" because that's purely a Linux term.
>
> Your DTS should accurately describe the hardware, not drivers. Then
> drivers can do whatever they want with it - have safe, non-concurrent
> access or keep poking same registers and break things...

The way the HW shall be described in DT is tightly coupled to the way 
the drivers will work on mapping the IO addresses.

There are 3 ways to describe the HW as far as I see it from address 
point of view: (actually 2 as option 3 is not really sane)

1) one big chunk of registers

2) smaller chunk of registers aiming to have each chunk describe a 
subset of the HW capablity (e.g. RAS, e.g. Refresh-rate, ...)

3) describe each register with its name

Each option dictate how driver shall map the address space.


If option 1 is chosen, then we shall have 2 drivers with same reg 
description.

For that case, they can both remap the whole space or each one can try 
to map only the section it needs.

If option 2 is chosen, then each driver can use DT to know exactly what 
it needs to map and do it in safer manner.


>
>> e.g. the EDAC driver needs register 0,1,2,4,5 and refresh-rate needs
>> register 3.
> I don't think there is EDAC and "refresh-rate" hardwares. There is
> memory controller.
>
>> If we would only have EDAC driver than we would do IO address mapping
>> from 0 with size 5 (not caring mapping register 3 even that its not used).
>>
>> However, with the other driver (refresh rate) that need register 3 we am
>> facing a problem.
>>
>> So looking for the best solution here.
>>
>> I don't think this is a problem that is specific to drivers/edac and to
>> drivers/memory, however, due to the nature of those two libraries this
>> conflict is more expected.
> All these problems look like started from wrong hardware description, so
> not sure if it is worth fixing something where the basis is already not
> correct.
>
> Best regards,
> Krzysztof
>