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From:   Michael Walle <michael@walle.cc>
To:     jszhang@kernel.org
Cc:     aou@eecs.berkeley.edu, conor@kernel.org,
        devicetree@vger.kernel.org, gregkh@linuxfoundation.org,
        ilpo.jarvinen@linux.intel.com, jirislaby@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
        linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
        palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org,
        Michael Walle <michael@walle.cc>
Subject: Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree
Date:   Wed,  4 Jan 2023 09:32:04 +0100
Message-Id: <20230104083204.1865526-1-michael@walle.cc>
In-Reply-To: <20221127132448.4034-7-jszhang@kernel.org>
References: <20221127132448.4034-7-jszhang@kernel.org>
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Hi,

> +		uart0: serial@30002000 {

According to the reference manual of the bl808, this is uart3. Can we also
use that name here?

> +			compatible = "bouffalolab,bl808-uart";
> +			reg = <0x30002000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&xtal>;

This is a shortcut and is likely to change in the future. The xtal
isn't really connected to the uart block, but instead there is a
clock mux and clock gate in between.

> +			status = "disabled";
> +		};

Thanks,
-michael