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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j4-20020a170902758400b00186dcc37df6si28739109pll.616.2023.01.04.01.23.36; Wed, 04 Jan 2023 01:23:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=RByDVmop; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233932AbjADJOx (ORCPT + 57 others); Wed, 4 Jan 2023 04:14:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233945AbjADJOo (ORCPT ); Wed, 4 Jan 2023 04:14:44 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D53BFD2B for ; Wed, 4 Jan 2023 01:14:44 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A9FAA61601 for ; Wed, 4 Jan 2023 09:14:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E34EC433D2; Wed, 4 Jan 2023 09:14:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672823683; bh=mJh49gOowpFn7+Mf2+NzoeE+1uPAP7nf0ykY5SI6xRA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=RByDVmopxsAX67RDoyuA2IWr4HOq9FpatqPtVszFPzZaebwXr8veU4HeQEgrtxf1I Q8uE8wYYZgIAWKjnm8AdHQkkG6bHfGP7z+YnIrOYwjHdiHAroKTiUwRLYkqZJBOF8w AKkmncuAsR8KBxgRCazMKMYiIO8v62KucjLHnMrYSvpSKZWtbdlxDSM+08P4LeymNH a6NoLvBYDb/dfLIAmIwpTkwjMWjtRL9BUKHn0L/JieiRjIhfi7oX3HvB5mqceAvm/B 6omlv6sF2XQc9fPfP4Rd1M7QXguLWpQWZwWvGSPNkne4ZsenZHRgb8SUi0gTdcI5+8 6XonmoREJZLlA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pCzr6-00GiDV-PE; Wed, 04 Jan 2023 09:14:40 +0000 Date: Wed, 04 Jan 2023 09:14:40 +0000 Message-ID: <86sfgq7jb3.wl-maz@kernel.org> From: Marc Zyngier To: Shanker Donthineni Cc: Catalin Marinas , Will Deacon , James Morse , , Subject: Re: [PATCH v2] arm64: gic: increase the number of IRQ descriptors In-Reply-To: <20230104023738.1258925-1-sdonthineni@nvidia.com> References: <20230104023738.1258925-1-sdonthineni@nvidia.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sdonthineni@nvidia.com, catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 04 Jan 2023 02:37:38 +0000, Shanker Donthineni wrote: > > The default value of NR_IRQS is not sufficient to support GICv4.1 > features and ~56K LPIs. This parameter would be too small for certain > server platforms where it has many IO devices and is capable of > direct injection of vSGI and vLPI features. > > Currently, maximum of 64 + 8192 (IRQ_BITMAP_BITS) IRQ descriptors > are allowed. The vCPU creation fails after reaching count ~400 with > kvm-arm.vgic_v4_enable=1. > > This patch increases NR_IRQS to 1^19 to cover 56K LPIs and 262144 > vSGIs (16K vPEs x 16). > > Signed-off-by: Shanker Donthineni > --- > Changes since v1: > -create from v6.2-rc1 and edit commit text > > arch/arm64/include/asm/irq.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h > index fac08e18bcd5..3fffc0b8b704 100644 > --- a/arch/arm64/include/asm/irq.h > +++ b/arch/arm64/include/asm/irq.h > @@ -4,6 +4,10 @@ > > #ifndef __ASSEMBLER__ > > +#if defined(CONFIG_ARM_GIC_V3_ITS) > +#define NR_IRQS (1 << 19) > +#endif > + > #include > > struct pt_regs; Sorry, but I don't think this is an acceptable change. This is a large overhead that affects *everyone*, and that will eventually be too small anyway with larger systems and larger interrupt spaces. A better way to address this would be to move to a more dynamic allocation, converting the irqdesc rb-tree into an xarray, getting rid of the bitmaps (the allocation bitmap and the resend one), and track everything in the xarray. This would scale, avoid allocations, and benefit all architectures. Thanks, M. -- Without deviation from the norm, progress is not possible.