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Date:   Wed, 4 Jan 2023 12:18:28 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Sudeep Holla <sudeep.holla@arm.com>
Cc:     Leyfoon Tan <leyfoon.tan@starfivetech.com>,
        Andrew Jones <ajones@ventanamicro.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Ley Foon Tan <lftan.linux@gmail.com>
Subject: Re: [PATCH] riscv: Move call to init_cpu_topology() to later
 initialization stage
Message-ID: <Y7VulIcGwuXvBES6@spud>
References: <20230103035316.3841303-1-leyfoon.tan@starfivetech.com>
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Hey Sudeep,

On Wed, Jan 04, 2023 at 10:49:00AM +0000, Sudeep Holla wrote:
> On Wed, Jan 04, 2023 at 09:49:48AM +0000, Conor Dooley wrote:
>=20
> [...]
>=20
> > >> Uhh, so where did this "capacity-dmips-mhz" property actually come f=
rom?
> > >> I had a quick check of qemu with grep & I don't see anything there t=
hat
> > >> would add this property.
> > >> This property should not be valid on anything other than arm AFAICT.
> > >
> > >This DT parameter is not in default Qemu. I've added it for testing (s=
ee test steps in below).=20
> > >This is preparation to support asymmetric CPU topology for RISC-V.
> >=20
> > The property is only valid on arm, so how does arm64 deal with such
> > asymmetric topologies without it?
>=20
> I don't think we can deal with asymmetric topologies without this.
> Yes we can detect the difference in the CPU types but we can only assume
> there are symmetric in terms of performance in absence of this property.


I looked at the bindings for it and forgot that the arm directory of
bindings applies to both arm and arm64. I see now that it is also used
on arm64.

>=20
> > Why should we "fix" something that may never be a valid dts?
> >
>=20
> I would not say invalid. But surely absence of it must be handled and
> we do that for sure. IIRC, here the presence of it is causing the issue.
> And if it is present means someone is trying to build it(I do understand
> this is Qemu but is quite common these days for power and performance
> balance in many SoC)

I said "invalid" as the binding is defined for arm{,64} in arm/cpus.yaml
& documented in the same directory in cpu-capacity.txt, but not yet on
riscv. All bets are off if your cpu node is using invalid properties
IMO, at least this one will fail to boot!

However, I see no reason (at this point) that we should deviate from
what arm{,64} is doing & that documenation should probably move to a
shared location at some point.

> > >>=20
> > >> I know arm64 does this, but there is any real reason for us to do so?
> > >> @Sudeep, do you know why arm64 calls that each time?
> >=20
> > I got myself mixed up between places I fiddled with storing the topolog=
y, so you can ignore that question Sudeep.
> > Clearly it's the one in smp_callin() that gets called for each CPU.
> > Woops.
> >=20
>=20
> Hmm I should have read all the messages in the thread. Doing by date/time
> didn't work well for me =F0=9F=98=84.

Meh, my fault for getting confused ;)

> > >> Or if it is worth "saving" that call on riscv, since arm64 is clearl=
y happily calling
> > >> it for many years & calling it later would likely head off a good fe=
w allocation
> > >> issues (like the one we saw with the topology reworking a few months=
 ago).
> >=20
> > ...but is it still worth moving the function call later to head off any=
 allocation failures if core topology code changes?
> >
>=20
> Agreed, given how we faced similar issues with cacheinfo on few RISC-V
> platforms.

Sweet, sounds like a plan to me. I'll go suggest some commit message
re-wording I think.

Thanks Sudeep!


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