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Date:   Wed, 4 Jan 2023 13:24:44 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Sudeep Holla <sudeep.holla@arm.com>
Cc:     Leyfoon Tan <leyfoon.tan@starfivetech.com>,
        Andrew Jones <ajones@ventanamicro.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Ley Foon Tan <lftan.linux@gmail.com>
Subject: Re: [PATCH] riscv: Move call to init_cpu_topology() to later
 initialization stage
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On Wed, Jan 04, 2023 at 12:56:32PM +0000, Sudeep Holla wrote:
> On Wed, Jan 04, 2023 at 12:18:28PM +0000, Conor Dooley wrote:

> > On Wed, Jan 04, 2023 at 10:49:00AM +0000, Sudeep Holla wrote:
> > > On Wed, Jan 04, 2023 at 09:49:48AM +0000, Conor Dooley wrote:

> > > > Why should we "fix" something that may never be a valid dts?
> > > >
> > >=20
> > > I would not say invalid. But surely absence of it must be handled and
> > > we do that for sure. IIRC, here the presence of it is causing the iss=
ue.
> > > And if it is present means someone is trying to build it(I do underst=
and
> > > this is Qemu but is quite common these days for power and performance
> > > balance in many SoC)
> >=20
> > I said "invalid" as the binding is defined for arm{,64} in arm/cpus.yaml
> > & documented in the same directory in cpu-capacity.txt, but not yet on
> > riscv. All bets are off if your cpu node is using invalid properties
> > IMO, at least this one will fail to boot!
> >=20
> > However, I see no reason (at this point) that we should deviate from
> > what arm{,64} is doing & that documenation should probably move to a
> > shared location at some point.
> >
>=20
> I prefer making this binding generic rather than patching to handle RISC-V
> differently in the generic code. Since it is optional, the platform
> need not use it if it is not needed.

Oh yeah, I was not suggesting making changes in the generic code. We
just need to change our cpu binding to match the arm cpu binding so that
having this property is accepted.

I shall go do that at some point today probably.

Thanks,
Conor.


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