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From:   Conor Dooley <conor@kernel.org>
To:     palmer@dabbelt.com
Cc:     conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
        Ley Foon Tan <leyfoon.tan@starfivetech.com>,
        Sudeep Holla <sudeep.holla@arm.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Jonathan Corbet <corbet@lwn.net>, Alex Shi <alexs@kernel.org>,
        Yanteng Si <siyanteng@loongson.cn>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org
Subject: [PATCH v1 0/2] dt-bindings: Add a cpu-capacity property for RISC-V
Date:   Wed,  4 Jan 2023 18:05:12 +0000
Message-Id: <20230104180513.1379453-1-conor@kernel.org>
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From: Conor Dooley <conor.dooley@microchip.com>

Hey,

Ever since RISC-V starting using generic arch topology code, the code
paths for cpu-capacity have been there but there's no binding defined to
actually convey the information. Defining the same property as used on
arm seems to be the only logical thing to do, so do it.

It's worth noting that right now, actually putting this property in a DT
will cause allocation failures on RISC-V - but there's already a patch
for that thanks to Ley Foon Tan:
https://patchwork.kernel.org/project/linux-riscv/patch/20230103035316.3841303-1-leyfoon.tan@starfivetech.com/

Thanks,
Conor.

CC: Ley Foon Tan <leyfoon.tan@starfivetech.com>
CC: Sudeep Holla <sudeep.holla@arm.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Conor Dooley <conor@kernel.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Alex Shi <alexs@kernel.org>
CC: Yanteng Si <siyanteng@loongson.cn>
CC: Lorenzo Pieralisi <lpieralisi@kernel.org>
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-riscv@lists.infradead.org
CC: linux-doc@vger.kernel.org

Conor Dooley (2):
  dt-bindings: arm: move cpu-capacity to a shared loation
  dt-bindings: riscv: add a capacity-dmips-mhz cpu property

 Documentation/devicetree/bindings/arm/cpus.yaml             | 2 +-
 .../devicetree/bindings/{arm => cpu}/cpu-capacity.txt       | 4 ++--
 Documentation/devicetree/bindings/riscv/cpus.yaml           | 6 ++++++
 Documentation/scheduler/sched-capacity.rst                  | 2 +-
 .../translations/zh_CN/scheduler/sched-capacity.rst         | 2 +-
 5 files changed, 11 insertions(+), 5 deletions(-)
 rename Documentation/devicetree/bindings/{arm => cpu}/cpu-capacity.txt (98%)

-- 
2.39.0