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Date:   Wed, 4 Jan 2023 23:29:06 +0100
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Subject: Re: [PATCH] clocksource/drivers/riscv: Increase the clock source
 rating
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To:     Samuel Holland <samuel@sholland.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Thomas Gleixner <tglx@linutronix.de>
Cc:     Prabhakar Lad <prabhakar.csengg@gmail.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
References: <20221228004444.61568-1-samuel@sholland.org>
From:   Daniel Lezcano <daniel.lezcano@linaro.org>
In-Reply-To: <20221228004444.61568-1-samuel@sholland.org>
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On 28/12/2022 01:44, Samuel Holland wrote:
> RISC-V provides an architectural clock source via the time CSR. This
> clock source exposes a 64-bit counter synchronized across all CPUs.
> Because it is accessed using a CSR, it is much more efficient to read
> than MMIO clock sources. For example, on the Allwinner D1, reading the
> sun4i timer in a loop takes 131 cycles/iteration, while reading the
> RISC-V time CSR takes only 5 cycles/iteration.
> 
> Adjust the RISC-V clock source rating so it is preferred over the
> various platform-specific MMIO clock sources.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
Applied, thanks

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