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From:   Leyfoon Tan <leyfoon.tan@starfivetech.com>
To:     Conor Dooley <conor@kernel.org>,
        "palmer@dabbelt.com" <palmer@dabbelt.com>
CC:     Conor Dooley <conor.dooley@microchip.com>,
        Sudeep Holla <sudeep.holla@arm.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Jonathan Corbet <corbet@lwn.net>,
        "Alex Shi" <alexs@kernel.org>, Yanteng Si <siyanteng@loongson.cn>,
        "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>
Subject: RE: [PATCH v1 2/2] dt-bindings: riscv: add a capacity-dmips-mhz cpu
 property
Thread-Topic: [PATCH v1 2/2] dt-bindings: riscv: add a capacity-dmips-mhz cpu
 property
Thread-Index: AQHZIGc9BMS8YNU6e0GmWB/Wrj6HBK6PEFog
Date:   Thu, 5 Jan 2023 01:55:52 +0000
Message-ID: <e2241591f14e4e0aa92d33b2f8d78f75@EXMBX161.cuchost.com>
References: <20230104180513.1379453-1-conor@kernel.org>
 <20230104180513.1379453-3-conor@kernel.org>
In-Reply-To: <20230104180513.1379453-3-conor@kernel.org>
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> -----Original Message-----
> 
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") RISC-
> V has used the generic arch topology code, which provides for disparate CPU
> capacities. We never defined a binding to acquire this information from the
> DT though, so document the one already used by the generic arch topology
> code: "capacity-dmips-mhz".
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
> b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index c6720764e765..2480c2460759 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -114,6 +114,12 @@ properties:
>        List of phandles to idle state nodes supported
>        by this hart (see ./idle-states.yaml).
> 
> +  capacity-dmips-mhz:
> +    description:
> +      u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
> +      DMIPS/MHz, relative to highest capacity-dmips-mhz
> +      in the system.
> +
>  required:
>    - riscv,isa
>    - interrupt-controller
> --
> 2.39.0

Thanks Conor.

Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>

Regards
Ley Foon