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This change is required due to clock source change in ADSP enabled platforms. Signed-off-by: Srinivasa Rao Mandadapu Tested-by: Mohammad Rafi Shaik --- arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi index 2a619b4..175ed9c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi @@ -182,3 +182,11 @@ &lpasscc { qcom,adsp-pil-mode; }; + +&swr0 { + resets = <&lpasscc LPASS_AUDIO_SWR_RX_CGCR>; +}; + +&swr1 { + resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; +}; -- 2.7.4