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Date:   Thu, 05 Jan 2023 14:22:07 +0000
Message-ID: <86sfgpnjsg.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Yogesh Lal <quic_ylal@quicinc.com>
Cc:     <mark.rutland@arm.com>, <daniel.lezcano@linaro.org>,
        <tglx@linutronix.de>, <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>
Subject: Re: ERRATUM_858921 is broken on 5.15 kernel
In-Reply-To: <ca4679a0-7f29-65f4-54b9-c575248192f1@quicinc.com>
References: <ca4679a0-7f29-65f4-54b9-c575248192f1@quicinc.com>
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On Thu, 05 Jan 2023 13:33:48 +0000,
Yogesh Lal <quic_ylal@quicinc.com> wrote:
>=20
> Hi,
>=20
> We are observing issue on A73 core where ERRATUM_858921 is broken.
>=20
> On 5.15 kernel arch_timer_enable_workaround is set by reading
> arm64_858921_read_cntpct_el0 and arm64_858921_read_cntvct_el0 during
> timer register using following path.

Have you checked whether the issue is still present on 6.1?

>=20
> arch_timer_enable_workaround->atomic_set(&timer_unstable_counter_workarou=
nd_in_use,
> 1);
>=20
> [code snap]
> 564 static
> 565 void arch_timer_enable_workaround(const struct
> arch_timer_erratum_workaround *wa,
> 566=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool local)
> 567 {
> 568=C2=A0=C2=A0=C2=A0=C2=A0 int i;
> 569
> 570=C2=A0=C2=A0=C2=A0=C2=A0 if (local) {
> 571 __this_cpu_write(timer_unstable_counter_workaround, wa);
> 572=C2=A0=C2=A0=C2=A0=C2=A0 } else {
> 573=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 for_each_possible_cpu(i)
> 574=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 per_cpu(timer_unstable_=
counter_workaround, i) =3D wa;
> 575=C2=A0=C2=A0=C2=A0=C2=A0 }
> 576
> 577=C2=A0=C2=A0=C2=A0=C2=A0 if (wa->read_cntvct_el0 || wa->read_cntpct_el=
0)
> 578 atomic_set(&timer_unstable_counter_workaround_in_use, 1);
>=20
>=20
> and based on above workaround enablement , appropriate function to get
> counter is used.
>=20
> 1008 static void __init arch_counter_register(unsigned type)
> 1009 {
> 1010=C2=A0=C2=A0=C2=A0=C2=A0 u64 start_count;
> 1011
> 1012=C2=A0=C2=A0=C2=A0=C2=A0 /* Register the CP15 based counter if we hav=
e one */
> 1013=C2=A0=C2=A0=C2=A0=C2=A0 if (type & ARCH_TIMER_TYPE_CP15) {
> 1014=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u64 (*rd)(void);
> 1015
> 1016=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if ((IS_ENABLED(CONF=
IG_ARM64) && !is_hyp_mode_available()) ||
> 1017=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 arch_timer_uses_ppi =3D=3D ARCH_TIMER_VIRT_PPI) {
> 1018=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 if (arch_timer_counter_has_wa())
> 1019=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 rd =3D arch_counter_get_cntvct_stable;
> 1020=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 else
> 1021=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 rd =3D arch_counter_get_cntvct;
> 1022=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } else {
> 1023=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 if (arch_timer_counter_has_wa())
> 1024=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 rd =3D arch_counter_get_cntpct_stable;
> 1025=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 else
> 1026=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 rd =3D arch_counter_get_cntpct;
> 1027=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }
> [snap]
> 1043 =C2=A0=C2=A0=C2=A0 /* 56 bits minimum, so we assume worst case rollo=
ver */
> 1044 =C2=A0=C2=A0=C2=A0 sched_clock_register(arch_timer_read_counter, 56,=
 arch_timer_rate);
>=20
>=20
> As our boot cores are not impacted by errata sched_clock_register()
> will register !arch_timer_counter_has_wa() callback.
>=20
> Now when errata impacted core boots up and sched_clock_register
> already register will !arch_timer_counter_has_wa() path.
> As sched_clock_register is not per_cpu bases so
> arch_timer_read_counter will always point to
> !arch_timer_counter_has_wa() function calls.

Please try the following hack, only compile tested as I do not have
access to any affected HW, and report whether this solves your issue
or not. Note that this is based on 6.2-rc2.

Thanks,

	M.

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm=
_arch_timer.c
index e09d4427f604..a7cf0a2c86d3 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -230,6 +230,28 @@ static u64 arch_counter_read_cc(const struct cyclecoun=
ter *cc)
 	return arch_timer_read_counter();
 }
=20
+static bool arch_timer_counter_has_wa(void);
+
+static u64 (*arch_counter_get_read_fn(void))(void)
+{
+	u64 (*rd)(void);
+
+	if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
+	    arch_timer_uses_ppi =3D=3D ARCH_TIMER_VIRT_PPI) {
+		if (arch_timer_counter_has_wa())
+			rd =3D arch_counter_get_cntvct_stable;
+		else
+			rd =3D arch_counter_get_cntvct;
+	} else {
+		if (arch_timer_counter_has_wa())
+			rd =3D arch_counter_get_cntpct_stable;
+		else
+			rd =3D arch_counter_get_cntpct;
+	}
+
+	return rd;
+}
+
 static struct clocksource clocksource_counter =3D {
 	.name	=3D "arch_sys_counter",
 	.id	=3D CSID_ARM_ARCH_COUNTER,
@@ -571,8 +593,10 @@ void arch_timer_enable_workaround(const struct arch_ti=
mer_erratum_workaround *wa
 			per_cpu(timer_unstable_counter_workaround, i) =3D wa;
 	}
=20
-	if (wa->read_cntvct_el0 || wa->read_cntpct_el0)
+	if (wa->read_cntvct_el0 || wa->read_cntpct_el0) {
 		atomic_set(&timer_unstable_counter_workaround_in_use, 1);
+		arch_timer_read_counter =3D arch_counter_get_read_fn();
+	}
=20
 	/*
 	 * Don't use the vdso fastpath if errata require using the
@@ -641,7 +665,7 @@ static bool arch_timer_counter_has_wa(void)
 #else
 #define arch_timer_check_ool_workaround(t,a)		do { } while(0)
 #define arch_timer_this_cpu_has_cntvct_wa()		({false;})
-#define arch_timer_counter_has_wa()			({false;})
+static bool arch_timer_counter_has_wa(void)		{ return false; }
 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
=20
 static __always_inline irqreturn_t timer_handler(const int access,
@@ -1079,22 +1103,7 @@ static void __init arch_counter_register(unsigned ty=
pe)
=20
 	/* Register the CP15 based counter if we have one */
 	if (type & ARCH_TIMER_TYPE_CP15) {
-		u64 (*rd)(void);
-
-		if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
-		    arch_timer_uses_ppi =3D=3D ARCH_TIMER_VIRT_PPI) {
-			if (arch_timer_counter_has_wa())
-				rd =3D arch_counter_get_cntvct_stable;
-			else
-				rd =3D arch_counter_get_cntvct;
-		} else {
-			if (arch_timer_counter_has_wa())
-				rd =3D arch_counter_get_cntpct_stable;
-			else
-				rd =3D arch_counter_get_cntpct;
-		}
-
-		arch_timer_read_counter =3D rd;
+		arch_timer_read_counter =3D arch_counter_get_read_fn();
 		clocksource_counter.vdso_clock_mode =3D vdso_default;
 	} else {
 		arch_timer_read_counter =3D arch_counter_get_cntvct_mem;

--=20
Without deviation from the norm, progress is not possible.