Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <0ff6e8f7-5dd4-a81f-9328-9e6d87837439@amd.com>
Date:   Thu, 5 Jan 2023 16:44:15 -0500
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101
 Thunderbird/102.6.1
Subject: Re: [PATCH v3] drm/amd/display: fix PSR-SU/DSC interoperability
 support
Content-Language: en-US
To:     Hamza Mahfooz <hamza.mahfooz@amd.com>,
        amd-gfx@lists.freedesktop.org
Cc:     Leo Li <sunpeng.li@amd.com>,
        Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
        Alex Deucher <alexander.deucher@amd.com>,
        =?UTF-8?Q?Christian_K=c3=b6nig?= <christian.koenig@amd.com>,
        "Pan, Xinhui" <Xinhui.Pan@amd.com>,
        David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        Anthony Koo <Anthony.Koo@amd.com>,
        David Zhang <dingchen.zhang@amd.com>,
        Po Ting Chen <robin.chen@amd.com>,
        Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>,
        Shirish S <shirish.s@amd.com>, Alex Hung <alex.hung@amd.com>,
        Pavle Kotarac <Pavle.Kotarac@amd.com>,
        Robin Chen <po-tchen@amd.com>,
        Camille Cho <Camille.Cho@amd.com>,
        dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
References: <20230105203353.378805-1-hamza.mahfooz@amd.com>
From:   Harry Wentland <harry.wentland@amd.com>
In-Reply-To: <20230105203353.378805-1-hamza.mahfooz@amd.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?Q2g2UmVvR1ltcGpwQUZ4d3NLMy9VUU41ZmtjMk05MTdPL0d0SDFLUThyQXl2?=
 =?utf-8?B?ZHZvbjJPWU1VNFpWZnVycFF1VkFIRjZWT2IzVEdvWE5qcitGdzlZVytDcWNh?=
 =?utf-8?B?RlRBdmdTdUdQNUVlbEExQW92eml2THNLRllmQzdIdWQ5alJQK1hobXN5d0VC?=
 =?utf-8?B?Y3RUdnpCc00rNk9lQTc2dHczYXFtZXJkb2RUSk1xU0hiVlVVUXNBci8zdEU2?=
 =?utf-8?B?bklZWXFWLzJxQzZGdFVHNXFQTWs1RnNOYmNGMFhWYU5VK2pWR3hrejJTKzNr?=
 =?utf-8?B?Ujh1d2ZBcFNRck05bkNuV2l1c2VEK2NWYTZHbnFBanJRL1AzamhrLzN1ZzZM?=
 =?utf-8?B?Skd1SVRnajY2VkJ2ejJRb1JOU2NZc1BVMnl2WHBJdEZtQ0crN1dHWFVETzVE?=
 =?utf-8?B?azZaZVpod0diZGxoNmNta0ttUG93MjRmWmVZV0lhOWpDVDZYMHJ4VXBzVlpY?=
 =?utf-8?B?cmJkRkN2K1daRWI5a3lDblV1YjRjQjBROE50WkEvSlNXS280N2dKL0ZEM1lr?=
 =?utf-8?B?akVUNUtQTjFKVjVBcFRYVU1aVzVycmtzbmpQNDAxSnc0SUp5NnZ6cG9VNGUv?=
 =?utf-8?B?RndyVitRejhndlp5QWlDT0JBY3VNOC82dXpEbVlUUzZIc3pZUTM2aktRNjlZ?=
 =?utf-8?B?S0dNM1dtZW5OdmN5dUsyakozZjhzWmJiSjYxbG8vU2wwd1lTWkZHSkcxYWl1?=
 =?utf-8?B?R1dmUVppdmRvMTArcVlaUDQrVDRaTWdHa2xiUHMyMkxZLzBvU29GSDloOVRD?=
 =?utf-8?B?NUpBTXBlMVczbWdvdTVydEIrWVZqM2dReUk5ejFtVVRzK2FhdEJhdEFPMVli?=
 =?utf-8?B?WWcyaGxaSlBadnRiNXJVYlVYTFpoMXBkT2pzc2pRWlFmNzludTZESVc4U1Fx?=
 =?utf-8?B?T090SG1kdTBhUHBVR0p0bXRFWW5yRllIRnMrT2pJb0kyVTZ4VEs1V3lsV2w3?=
 =?utf-8?B?NGZHYUlqTW9yTXZRdGFPUXpERFhqQ2dLUWVkL1kvMkNkU0xiTXkwaXRLWWhB?=
 =?utf-8?B?eStLMWwzbk1BdVQ4OWFBK2hRSUNEVEErNGtKNTlyek1OOTJuMVZUc2JRUCtu?=
 =?utf-8?B?Q05HN2h0a2ZTZzdWano0eG1IUmp3bzBzWWFRVXZsYnh3VnM4OVFINzZVb3kw?=
 =?utf-8?B?ZjNPOTlqT0hqcldXSGswbStOZnJUUmRrQ3BGbEdYY3BkRTFEa0ZIRFp4S2lP?=
 =?utf-8?B?M2QyRldhTHJRWm03M1IyWmcyYml1YVhIU3BHb1EwL1JLOUZSRDliNUUxTjBJ?=
 =?utf-8?B?R3F2cm00QWFJWDJoK1AwbS9uWVFscENQZU04MGNLeEp2b09aWjkrbEl6RGhk?=
 =?utf-8?B?elM1bkFkcjc0L1BYaFZCMk9JVFRaelgxV0VlUzJWQUlNVmlzZ0JDNzhwTzMx?=
 =?utf-8?B?ZWJWL256M0h3Qk56OTNrNmxqcnFMbFQ0MjgyZXZVNU9jVW9kaDBrd012eWsy?=
 =?utf-8?B?dTVmVjJNZUpLd29YaytrWmNHbmxwaTlkSWVpRjZwYlBSQmlWeWJFdy8rbWFv?=
 =?utf-8?B?SHAyUTRNeHlCN3FmMkdZRHRKRjcwdHZOSEVTeU5MK0tDVU9OalEwNFlBaGxl?=
 =?utf-8?B?QzREK09FMTVRSmJyVmY5U1paUFlvZEdpQkVlUW9hMkhpQ2w3a3c4NTg5L1Vu?=
 =?utf-8?B?WWN2YlZBL3hNVENvYmJFek5nVnQwOThMb0twK2l3SEVLaVBnRXJNRHB5T01H?=
 =?utf-8?B?cEdzaGJsZVY3ak9STkE4T0tTUWRVb2Njd2MxUm4wWExBNGdWa3ZoaThRL3Rq?=
 =?utf-8?B?bWMxR0lJaXhmYmVFZ3ZRWVZGdW5JTUFwMFliN2tDMGM4UXRIeXRDVGxxM2pp?=
 =?utf-8?B?TXZtRDFZT3ZrL2pucnYxUGdZWFJBWit4citVUGUwbmgwOHkybE9tcjRSa0RC?=
 =?utf-8?B?M1lZTVlUV2RXY1p3aDNvUDIzK3E3R1BiUWlIMEtlcmpPR245d2dNWEZJRFBz?=
 =?utf-8?B?a09yR2tWUEd3MktnTTR3R09CR1FSOFRYa3FXVVlmbk11cjVYMkdFVG9HWU96?=
 =?utf-8?B?S1B1Rzh4MDMzbDlQUDR6VXNiM2lwR0liNTZ0RlpIbE0yOThseVI4N3pob0dT?=
 =?utf-8?B?VElmVHJoU2Zxc0pDb2UxbE9mQVRteVNWZUpmTzZWaVJwd2RZOXExNW5ERmxT?=
 =?utf-8?Q?l7p58C0B00YK1IcsZsaFxLHAm?=
X-OriginatorOrg: amd.com
X-MS-Exchange-CrossTenant-Network-Message-Id: e1864c02-3c3d-4818-6382-08daef660132
X-MS-Exchange-CrossTenant-AuthSource: CO6PR12MB5427.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 21:44:21.3704
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: +OC86wLjEvJpzlhXkTsXC31jxLdxVymKl6+dXrvGUWB4sNjv/D53PrzxOpBNlXhsSeO5hpGnjLT0VbEnoKYt5w==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6674
X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,
        RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham
        autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 1/5/23 15:33, Hamza Mahfooz wrote:
> Currently, there are issues with enabling PSR-SU + DSC. This stems from
> the fact that DSC imposes a slice height on transmitted video data and
> we are not conforming to that slice height in PSR-SU regions. So, pass
> slice_height into su_y_granularity to feed the DSC slice height into
> PSR-SU code.
> 
> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>

Acked-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ---
> v2: move code to modules/power.
> v3: use ASSERT() instead of WARN() and add a condition that clarifies
>     that PSR-SU + DSC can only be enabled on an eDP connection.
> ---
>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  3 ++
>  .../amd/display/modules/power/power_helpers.c | 31 +++++++++++++++++++
>  .../amd/display/modules/power/power_helpers.h |  3 ++
>  3 files changed, 37 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
> index 26291db0a3cf..872d06fe1436 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
> @@ -122,6 +122,9 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
>  		psr_config.allow_multi_disp_optimizations =
>  			(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
>  
> +		if (!psr_su_set_y_granularity(dc, link, stream, &psr_config))
> +			return false;
> +
>  		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
>  
>  	}
> diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
> index 9b5d9b2c9a6a..381f708ef756 100644
> --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
> +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
> @@ -916,3 +916,34 @@ bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_s
>  {
>  	return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);
>  }
> +
> +bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link,
> +			      struct dc_stream_state *stream,
> +			      struct psr_config *config)
> +{
> +	uint16_t pic_height;
> +	uint8_t slice_height;
> +
> +	if (!dc->caps.edp_dsc_support ||
> +	    link->panel_config.dsc.disable_dsc_edp ||
> +	    !link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
> +	    !(link->connector_signal & SIGNAL_TYPE_EDP) ||
> +	    !stream->timing.dsc_cfg.num_slices_v)
> +		return true;
> +
> +	pic_height = stream->timing.v_addressable +
> +		stream->timing.v_border_top + stream->timing.v_border_bottom;
> +	slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
> +
> +	if (slice_height) {
> +		if (config->su_y_granularity &&
> +		    (slice_height % config->su_y_granularity)) {
> +			ASSERT(0);
> +			return false;
> +		}
> +
> +		config->su_y_granularity = slice_height;
> +	}
> +
> +	return true;
> +}
> diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
> index 316452e9dbc9..bb16b37b83da 100644
> --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
> +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
> @@ -59,4 +59,7 @@ void mod_power_calc_psr_configs(struct psr_config *psr_config,
>  		const struct dc_stream_state *stream);
>  bool mod_power_only_edp(const struct dc_state *context,
>  		const struct dc_stream_state *stream);
> +bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link,
> +			      struct dc_stream_state *stream,
> +			      struct psr_config *config);
>  #endif /* MODULES_POWER_POWER_HELPERS_H_ */