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From:   Yipeng Zou <zouyipeng@huawei.com>
To:     <tglx@linutronix.de>, <maz@kernel.org>,
        <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>
CC:     <hewenliang4@huawei.com>, <zouyipeng@huawei.com>,
        <chris.zjh@huawei.com>, <liaochang1@huawei.com>
Subject: [RFC PATCH] irqchip/gic-v3: wait irq done to set affinity
Date:   Fri, 6 Jan 2023 16:21:36 +0800
Message-ID: <20230106082136.68501-1-zouyipeng@huawei.com>
MIME-Version: 1.0
Content-Type: text/plain
Precedence: bulk

Recently we have some problem about gic set affinity in our test.

This patch just aim to make some discuss about this problem.

For now, the implementation of gic set affinity going to take effects
immediately, and without check if any irq are being processed.

So, This leads to some problem, think about this scenario:

1. First, we have an irq was generated by an device.

2. In the processing of this irq(after handle event, before clear
IRQD_IRQ_INPROGRESS flag), we modify the route and the gic takes effect
immediately,at the same time the new one was generated again.

3. The new irq will be processing in other cpu which different form the
old one.

4. The new irq going to be discarded because of the flag IRQD_IRQ_INPROGRESS
has been set.

I notice that if we set IRQF_ONESHOT when register the irq, this problem
will gone.

But I'm also thinking about change the gic_set_affinity function, to wait
current irq done on all cpus before gic_write_irouter.
I'm not sure if that's appropriate.

Is the best workaround to use IRQF_ONESHOT to prevent reentrancy?

Please let me know, if have any other suggestions on this issue.

Signed-off-by: Yipeng Zou <zouyipeng@huawei.com>
---
 drivers/irqchip/irq-gic-v3.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 997104d4338e..e9b9f15f07f8 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1348,6 +1348,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 	reg = gic_dist_base(d) + offset + (index * 8);
 	val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
 
+	// wait irq done on all cpus
+
 	gic_write_irouter(val, reg);
 
 	/*
-- 
2.17.1