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Reply-To: Sean Christopherson <seanjc@google.com>
Date:   Sat,  7 Jan 2023 01:10:19 +0000
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Message-ID: <20230107011025.565472-1-seanjc@google.com>
Subject: [PATCH 0/6] KVM: x86: x2APIC reserved bits/regs fixes
From:   Sean Christopherson <seanjc@google.com>
To:     Sean Christopherson <seanjc@google.com>,
        Paolo Bonzini <pbonzini@redhat.com>
Cc:     kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
        Marc Orr <marcorr@google.com>, Ben Gardon <bgardon@google.com>,
        Venkatesh Srinivas <venkateshs@chromium.org>
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Fixes for edge cases where KVM mishandles reserved bits/regs checks when
the vCPU is in x2APIC mode.

The first two patches were previously posted[*], but both patches were
broken (as posted against upstream), hence I took full credit for doing
the work and changed Marc to a reporter.

The VMX APICv fixes are for bugs found when writing tests.  *sigh*
I didn't Cc those to stable as the odds of breaking something when touching
the MSR bitmaps seemed higher than someone caring about a 10 year old bug.

AMD x2AVIC support may or may not suffer similar interception bugs, but I
don't have hardware to test and this already snowballed further than
expected...

[*] https://lore.kernel.org/kvm/20220525173933.1611076-1-venkateshs@chromium.org

Sean Christopherson (6):
  KVM: x86: Inject #GP if WRMSR sets reserved bits in APIC Self-IPI
  KVM: x86: Inject #GP on x2APIC WRMSR that sets reserved bits 63:32
  KVM: x86: Mark x2APIC DFR reg as non-existent for x2APIC
  KVM: x86: Split out logic to generate "readable" APIC regs mask to
    helper
  KVM: VMX: Always intercept accesses to unsupported "extended" x2APIC
    regs
  KVM: VMX: Intercept reads to invalid and write-only x2APIC registers

 arch/x86/kvm/lapic.c   | 55 ++++++++++++++++++++++++++----------------
 arch/x86/kvm/lapic.h   |  2 ++
 arch/x86/kvm/vmx/vmx.c | 40 +++++++++++++++---------------
 3 files changed, 57 insertions(+), 40 deletions(-)


base-commit: 91dc252b0dbb6879e4067f614df1e397fec532a1
-- 
2.39.0.314.g84b9a713c41-goog