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Date:   Sun, 8 Jan 2023 15:49:07 -0600
From:   Rob Herring <robh@kernel.org>
To:     Conor Dooley <conor@kernel.org>
Cc:     Alex Shi <alexs@kernel.org>, devicetree@vger.kernel.org,
        Yanteng Si <siyanteng@loongson.cn>,
        Ley Foon Tan <leyfoon.tan@starfivetech.com>,
        linux-kernel@vger.kernel.org, Sudeep Holla <sudeep.holla@arm.com>,
        linux-doc@vger.kernel.org, Jonathan Corbet <corbet@lwn.net>,
        linux-riscv@lists.infradead.org,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        palmer@dabbelt.com, Rob Herring <robh+dt@kernel.org>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v1 2/2] dt-bindings: riscv: add a capacity-dmips-mhz cpu
 property
Message-ID: <167321454620.325726.1419996484202189237.robh@kernel.org>
References: <20230104180513.1379453-1-conor@kernel.org>
 <20230104180513.1379453-3-conor@kernel.org>
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On Wed, 04 Jan 2023 18:05:14 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.")
> RISC-V has used the generic arch topology code, which provides for
> disparate CPU capacities. We never defined a binding to acquire this
> information from the DT though, so document the one already used by the
> generic arch topology code: "capacity-dmips-mhz".
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>