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References: <20230103141409.772298-1-apatel@ventanamicro.com>
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From:   Anup Patel <anup@brainfault.org>
Date:   Mon, 9 Jan 2023 10:39:08 +0530
Message-ID: <CAAhSdy2YKJfuxhBmsx9v-OMyxKQjys+J-z_ZqoPJF7q=YrE4Zw@mail.gmail.com>
Subject: Re: [PATCH v2 1/9] RISC-V: Add AIA related CSR defines
To:     Conor Dooley <conor@kernel.org>
Cc:     Anup Patel <apatel@ventanamicro.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Atish Patra <atishp@atishpatra.org>,
        Alistair Francis <Alistair.Francis@wdc.com>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org
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On Thu, Jan 5, 2023 at 4:37 AM Conor Dooley <conor@kernel.org> wrote:
>
> Hey Anup!
>
> On Tue, Jan 03, 2023 at 07:44:01PM +0530, Anup Patel wrote:
> > The RISC-V AIA specification improves handling per-HART local interrupts
> > in a backward compatible manner. This patch adds defines for new RISC-V
> > AIA CSRs.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> >  arch/riscv/include/asm/csr.h | 92 ++++++++++++++++++++++++++++++++++++
> >  1 file changed, 92 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> > index 0e571f6483d9..4e1356bad7b2 100644
> > --- a/arch/riscv/include/asm/csr.h
> > +++ b/arch/riscv/include/asm/csr.h
> > @@ -73,7 +73,10 @@
> >  #define IRQ_S_EXT            9
> >  #define IRQ_VS_EXT           10
> >  #define IRQ_M_EXT            11
> > +#define IRQ_S_GEXT           12
> >  #define IRQ_PMU_OVF          13
> > +#define IRQ_LOCAL_MAX                (IRQ_PMU_OVF + 1)
> > +#define IRQ_LOCAL_MASK               ((_AC(1, UL) << IRQ_LOCAL_MAX) - 1)
> >
> >  /* Exception causes */
> >  #define EXC_INST_MISALIGNED  0
> > @@ -156,6 +159,26 @@
> >                                (_AC(1, UL) << IRQ_S_TIMER) | \
> >                                (_AC(1, UL) << IRQ_S_EXT))
> >
> > +/* AIA CSR bits */
> > +#define TOPI_IID_SHIFT               16
> > +#define TOPI_IID_MASK                0xfff
> > +#define TOPI_IPRIO_MASK              0xff
> > +#define TOPI_IPRIO_BITS              8
> > +
> > +#define TOPEI_ID_SHIFT               16
> > +#define TOPEI_ID_MASK                0x7ff
> > +#define TOPEI_PRIO_MASK              0x7ff
> > +
> > +#define ISELECT_IPRIO0               0x30
> > +#define ISELECT_IPRIO15              0x3f
> > +#define ISELECT_MASK         0x1ff
> > +
> > +#define HVICTL_VTI           0x40000000
> > +#define HVICTL_IID           0x0fff0000
> > +#define HVICTL_IID_SHIFT     16
> > +#define HVICTL_IPRIOM                0x00000100
> > +#define HVICTL_IPRIO         0x000000ff
>
> Why not name these as masks, like you did for the other masks?
> Also, the mask/shift defines appear inconsistent. TOPI_IID_MASK is
> intended to be used post-shift AFAICT, but HVICTL_IID_SHIFT is intended
> to be used *pre*-shift.
> Some consistency in naming and function would be great.

The following convention is being followed in asm/csr.h for defining
MASK of any XYZ field in ABC CSR:
1. ABC_XYZ : This name is used for MASK which is intended
   to be used before SHIFT
2. ABC_XYZ_MASK: This name is used for MASK which is
   intended to be used after SHIFT

The existing defines for [M|S]STATUS, HSTATUS, SATP, and xENVCFG
follows the above convention. The only outlier is HGATPx_VMID_MASK
define which I will fix in my next KVM RISC-V series.

I don't see how any of the AIA CSR defines are violating the above
convention.

The choice of ABC_XYZ versus ABC_XYZ_MASK name is upto
the developer as long as the above convention is not violated.

>
>
> > +/* Machine-Level High-Half CSRs (AIA) */
> > +#define CSR_MIDELEGH         0x313
>
> I feel like I could find Midelegh in an Irish dictionary lol
> Anyways, I went through the CSRs and they do all seem correct.
>
> Thanks,
> Conor.
>
>

Regards,
Anup