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Date:   Mon, 9 Jan 2023 20:34:16 +0300
From:   Serge Semin <fancer.lancer@gmail.com>
To:     Sudip Mukherjee <sudip.mukherjee@sifive.com>
Cc:     Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        jude.onyenegecha@sifive.com, ben.dooks@sifive.com,
        jeegar.lakhani@sifive.com, linux-spi@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 04/15] spi: dw: add check for support of enhanced spi
Message-ID: <20230109173416.zzphzen7vnzsttsu@mobilestation>
References: <20221212180732.79167-1-sudip.mukherjee@sifive.com>
 <20221212180732.79167-5-sudip.mukherjee@sifive.com>
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In-Reply-To: <20221212180732.79167-5-sudip.mukherjee@sifive.com>
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On Mon, Dec 12, 2022 at 06:07:21PM +0000, Sudip Mukherjee wrote:
> Before doing the mem op, spi controller will be queried about the
> buswidths it supports. Add the dual/quad/octal if the controller
> has the DW_SPI_CAP_EMODE capability.
> The DW_SPI_CAP_EMODE capability will be enabled in a later patch.
> 
> Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com>
> ---
>  drivers/spi/spi-dw-core.c | 25 ++++++++++++++++++++++++-
>  drivers/spi/spi-dw.h      |  1 +
>  2 files changed, 25 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
> index d59401f16c47a..49fad58ceb94a 100644
> --- a/drivers/spi/spi-dw-core.c
> +++ b/drivers/spi/spi-dw-core.c
> @@ -510,6 +510,26 @@ static int dw_spi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op)
>  	return 0;
>  }
>  
> +static bool dw_spi_supports_enh_mem_op(struct spi_mem *mem,
> +				       const struct spi_mem_op *op)
> +{
> +	if (op->addr.nbytes != 0 && op->addr.buswidth != 1 &&
> +	    op->addr.buswidth != op->data.buswidth)
> +		return false;
> +
> +	if (op->cmd.buswidth != 1 && op->cmd.buswidth != op->addr.buswidth &&
> +	    op->cmd.buswidth != op->data.buswidth)
> +		return false;
> +
> +	if (op->dummy.nbytes != 0 && op->data.dir == SPI_MEM_DATA_OUT)
> +		return false;
> +
> +	if (op->dummy.nbytes != 0 && op->dummy.nbytes / op->dummy.buswidth > 4)
> +		return false;
> +
> +	return spi_mem_default_supports_op(mem, op);
> +}
> +
>  static bool dw_spi_supports_mem_op(struct spi_mem *mem,
>  				   const struct spi_mem_op *op)
>  {
> @@ -792,7 +812,10 @@ static void dw_spi_init_mem_ops(struct dw_spi *dws)

>  	if (!dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) &&
>  	    !dws->set_cs) {
>  		dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size;
> -		dws->mem_ops.supports_op = dw_spi_supports_mem_op;

Please see my comment to the cover letter. In order to have a more
readable method I'd suggest to convert it to something like this:

< dw_spi_init_mem_ops() {
< 	if (dws->mem_ops.exec_op || dws->caps & DW_SPI_CAP_CS_OVERRIDE ||
< 	    dws->set_cs)
<		return;
<
< 	if (dws->caps & DW_SPI_CAP_ENH_CLK_STR) {
< 		dws->mem_ops.adjust_op_size = dw_spi_enh_adjust_mem_op;
< 		dws->mem_ops.supports_op = dw_spi_enh_supports_mem_op;
< 		dws->mem_ops.exec_op = dw_spi_enh_exec_mem_op;
< 
<		return;
< 	}
<
<  	dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size;
< 	dws->mem_ops.supports_op = dw_spi_supports_mem_op;
< 	dws->mem_ops.exec_op = dw_spi_exec_mem_op;
<
<	return;
< }

> +		if (dws->caps & DW_SPI_CAP_EMODE)

Your implementation is working only if the clock-stretching feature is
available.

> +			dws->mem_ops.supports_op = dw_spi_supports_enh_mem_op;
> +		else
> +			dws->mem_ops.supports_op = dw_spi_supports_mem_op;
>  		dws->mem_ops.exec_op = dw_spi_exec_mem_op;
>  		if (!dws->max_mem_freq)
>  			dws->max_mem_freq = dws->max_freq;
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index f29d89d05f34b..327d037bdb10e 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -34,6 +34,7 @@
>  /* DW SPI controller capabilities */
>  #define DW_SPI_CAP_CS_OVERRIDE		BIT(0)
>  #define DW_SPI_CAP_DFS32		BIT(1)

> +#define DW_SPI_CAP_EMODE		BIT(2)

As I suggested in the cover letter let's make it DW_SPI_CAP_ENH (any
better suggestion?). Then the clock-stretching capability flag will be
DW_SPI_CAP_ENH_CLK_STR.

-Serge(y)

>  
>  /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
>  #define DW_SPI_CTRLR0			0x00
> -- 
> 2.30.2
>