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[83.9.2.45]) by smtp.gmail.com with ESMTPSA id c17-20020a056512325100b00499aefcf68esm1740155lfr.292.2023.01.09.10.29.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Jan 2023 10:29:08 -0800 (PST) Message-ID: <6f0a3f5a-186c-54ae-b43d-3aef13e91474@linaro.org> Date: Mon, 9 Jan 2023 19:29:06 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH 18/18] arm64: dts: qcom: add initial support for qcom sa8775p-ride Content-Language: en-US To: Bartosz Golaszewski , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Manivannan Sadhasivam , Jassi Brar , Linus Walleij , Catalin Marinas , Richard Cochran , Srinivas Kandagatla , Vinod Koul , Alex Elder Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-gpio@vger.kernel.org, netdev@vger.kernel.org, Bartosz Golaszewski References: <20230109174511.1740856-1-brgl@bgdev.pl> <20230109174511.1740856-19-brgl@bgdev.pl> From: Konrad Dybcio In-Reply-To: <20230109174511.1740856-19-brgl@bgdev.pl> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9.01.2023 18:45, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski > > This adds basic support for the Qualcomm sa8775p platform and the > reference board: sa8775p-ride. The dt files describe the basics of the > SoC and enable booting to shell. > > Signed-off-by: Bartosz Golaszewski > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 39 + > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 841 ++++++++++++++++++++++ > 3 files changed, 881 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts > create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index 3e79496292e7..39b8206f7131 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb > dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb > +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb > dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb > dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > new file mode 100644 > index 000000000000..d4dae32a84cc > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > @@ -0,0 +1,39 @@ > +// SPDX-License-Identifier: GPL-2.0-only BSD3? > +/* > + * Copyright (c) 2023, Linaro Limited > + */ > + > +/dts-v1/; > + > +#include "sa8775p.dtsi" > + > +/ { > + model = "Qualcomm SA8875P Ride"; > + compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; > + > + aliases { > + serial0 = &uart10; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&qupv3_id_1 { > + status = "okay"; > +}; > + > +&uart10 { > + compatible = "qcom,geni-debug-uart"; > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart10_state>; > +}; > + > +&tlmm { > + qup_uart10_state: qup_uart10_state { the node names (between ':' and '{') should end in -state, but the label does not have to. In fact, you'll probably want to have a "default" and a "sleep" state with different drive-strength and bias properties. > + pins = "gpio46", "gpio47"; > + function = "qup1_se3"; > + }; > +}; Missing xo rate override. > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > new file mode 100644 > index 000000000000..1a3b11628e38 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -0,0 +1,841 @@ > +// SPDX-License-Identifier: GPL-2.0-only BSD3? > +/* > + * Copyright (c) 2023, Linaro Limited > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + clocks { > + xo_board_clk: xo-board-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32764>; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + L2_0: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + L3_0: l3-cache { > + compatible = "cache"; > + }; > + }; > + }; > + > + CPU1: cpu@100 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + cpu-release-addr = <0x0 0x90000000>; > + next-level-cache = <&L2_1>; > + L2_1: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU2: cpu@200 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x200>; > + enable-method = "psci"; > + next-level-cache = <&L2_2>; > + L2_2: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU3: cpu@300 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x300>; > + enable-method = "psci"; > + next-level-cache = <&L2_3>; > + L2_3: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU4: cpu@10000 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10000>; > + enable-method = "psci"; > + next-level-cache = <&L2_4>; > + L2_4: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + L3_1: l3-cache { > + compatible = "cache"; > + }; > + > + }; > + }; > + > + CPU5: cpu@10100 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10100>; > + enable-method = "psci"; > + next-level-cache = <&L2_5>; > + L2_5: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + }; > + }; > + > + CPU6: cpu@10200 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10200>; > + enable-method = "psci"; > + next-level-cache = <&L2_6>; > + L2_6: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + }; > + }; > + > + CPU7: cpu@10300 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10300>; > + enable-method = "psci"; > + next-level-cache = <&L2_7>; > + L2_7: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + }; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + > + core2 { > + cpu = <&CPU2>; > + }; > + > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&CPU4>; > + }; > + > + core1 { > + cpu = <&CPU5>; > + }; > + > + core2 { > + cpu = <&CPU6>; > + }; > + > + core3 { > + cpu = <&CPU7>; > + }; > + }; > + }; On other SoCs we define a single DynamIQ cluster, is it something we should change? > + }; > + > + /* Will be updated by the bootloader. */ > + memory { The memory node should have a unit address, probably 0x80000000 in your case, but please doublecheck (for example by reading the value from /sys/firmware/) > + device_type = "memory"; > + reg = <0 0 0 0>; 0x0 please > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + sail_ss_mem: sail_ss_region@80000000 { No underscores in node names, use -s instead. > + no-map; > + reg = <0x0 0x80000000 0x0 0x10000000>; Please put reg above no-map. > + }; > + > + hyp_mem: hyp_region@90000000 { > + no-map; > + reg = <0x0 0x90000000 0x0 0x600000>; > + }; > + > + xbl_boot_mem: xbl_boot_region@90600000 { > + no-map; > + reg = <0x0 0x90600000 0x0 0x200000>; > + }; > + > + aop_image_mem: aop_image_region@90800000 { > + no-map; > + reg = <0x0 0x90800000 0x0 0x60000>; > + }; > + > + aop_cmd_db_mem: aop_cmd_db_region@90860000 { > + compatible = "qcom,cmd-db"; > + no-map; > + reg = <0x0 0x90860000 0x0 0x20000>; > + }; > + > + uefi_log: uefi_log_region@908b0000 { > + no-map; > + reg = <0x0 0x908b0000 0x0 0x10000>; > + }; > + > + reserved_mem: reserved_region@908f0000 { > + no-map; > + reg = <0x0 0x908f0000 0x0 0xf000>; > + }; > + > + secdata_apss_mem: secdata_apss_region@908ff000 { > + no-map; > + reg = <0x0 0x908ff000 0x0 0x1000>; > + }; > + > + smem_mem: smem_region@90900000 { > + compatible = "qcom,smem"; > + reg = <0x0 0x90900000 0x0 0x200000>; > + no-map; > + hwlocks = <&tcsr_mutex 3>; > + }; > + > + cpucp_fw_mem: cpucp_fw_region@90b00000 { > + no-map; > + reg = <0x0 0x90b00000 0x0 0x100000>; > + }; > + > + lpass_machine_learning_mem: lpass_machine_learning_region@93b00000 { > + no-map; > + reg = <0x0 0x93b00000 0x0 0xf00000>; > + }; > + > + adsp_rpc_remote_heap_mem: adsp_rpc_remote_heap_region@94a00000 { > + no-map; > + reg = <0x0 0x94a00000 0x0 0x800000>; > + }; > + > + pil_camera_mem: pil_camera_region@95200000 { > + no-map; > + reg = <0x0 0x95200000 0x0 0x500000>; > + }; > + > + pil_adsp_mem: pil_adsp_region@95c00000 { > + no-map; > + reg = <0x0 0x95c00000 0x0 0x1e00000>; > + }; > + > + pil_gdsp0_mem: pil_gdsp0_region@97b00000 { > + no-map; > + reg = <0x0 0x97b00000 0x0 0x1e00000>; > + }; > + > + pil_gdsp1_mem: pil_gdsp1_region@99900000 { > + no-map; > + reg = <0x0 0x99900000 0x0 0x1e00000>; > + }; > + > + pil_cdsp0_mem: pil_cdsp0_region@9b800000 { > + no-map; > + reg = <0x0 0x9b800000 0x0 0x1e00000>; > + }; > + > + pil_gpu_mem: pil_gpu_region@9d600000 { > + no-map; > + reg = <0x0 0x9d600000 0x0 0x2000>; > + }; > + > + pil_cdsp1_mem: pil_cdsp1_region@9d700000 { > + no-map; > + reg = <0x0 0x9d700000 0x0 0x1e00000>; > + }; > + > + pil_cvp_mem: pil_cvp_region@9f500000 { > + no-map; > + reg = <0x0 0x9f500000 0x0 0x700000>; > + }; > + > + pil_video_mem: pil_video_region@9fc00000 { > + no-map; > + reg = <0x0 0x9fc00000 0x0 0x700000>; > + }; > + > + hyptz_reserved_mem: hyptz_reserved_region@beb00000 { > + no-map; > + reg = <0x0 0xbeb00000 0x0 0x11500000>; > + }; > + > + tz_stat_mem: tz_stat_region@d0000000 { > + no-map; > + reg = <0x0 0xd0000000 0x0 0x100000>; > + }; > + > + tags_mem: tags_region@d0100000 { > + no-map; > + reg = <0x0 0xd0100000 0x0 0x1200000>; > + }; > + > + qtee_mem: qtee_region@d1300000 { > + no-map; > + reg = <0x0 0xd1300000 0x0 0x500000>; > + }; > + > + trusted_apps_mem: trusted_apps_region@d1800000 { > + no-map; > + reg = <0x0 0xd1800000 0x0 0x3900000>; > + }; > + > + dump_mem: mem_dump_region { > + compatible = "shared-dma-pool"; > + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; > + reusable; > + size = <0 0x3000000>; > + }; > + > + /* global autoconfigured region for contiguous allocations */ > + linux,cma { > + compatible = "shared-dma-pool"; > + alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; > + reusable; > + alignment = <0x0 0x400000>; > + size = <0x0 0x2000000>; > + linux,cma-default; > + }; Are you sure these last two are useful? > + }; > + > + psci { Top-level nodes should be sorted alphabetically. > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + firmware { > + scm { > + compatible = "qcom,scm"; This one should also have a SoC-specific compatible. > + }; > + }; > + > + qup_opp_table_100mhz: qup-100mhz-opp-table { > + compatible = "operating-points-v2"; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + > + soc: soc@0 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0 0xffffffff>; You probably want 36 or more bits of addressing here, otherwise SMMU translation will be playing jokes on you, cutting off some bits.. > + > + gcc: clock-controller@100000 { > + compatible = "qcom,gcc-sa8775p"; Please update the compatible after you update it in the .c driver. > + reg = <0x100000 0xc7018>; The GCC size is usually something more rounded to 0x1000, can you doublecheck? > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&sleep_clk>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, /* TODO: usb_0_ssphy */ > + <0>, > + <0>, > + <0>, > + <0>; > + power-domains = <&rpmhpd SA8775P_CX>; compatible reg clocks #clock-cells #reset-cells power-domains #power-domain-cells please > + }; > + > + ipcc: mailbox@408000 { > + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; > + reg = <0x408000 0x1000>; > + interrupts = ; > + interrupt-controller; > + #interrupt-cells = <3>; > + #mbox-cells = <2>; > + }; > + > + aggre1_noc:interconnect-aggre1-noc { > + compatible = "qcom,sa8775p-aggre1-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + aggre2_noc: interconnect-aggre2-noc { > + compatible = "qcom,sa8775p-aggre2-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + clk_virt: interconnect-clk-virt { > + compatible = "qcom,sa8775p-clk-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + config_noc: interconnect-config-noc { > + compatible = "qcom,sa8775p-config-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + dc_noc: interconnect-dc-noc { > + compatible = "qcom,sa8775p-dc-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + gem_noc: interconnect-gem-noc { > + compatible = "qcom,sa8775p-gem-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + gpdsp_anoc: interconnect-gpdsp-anoc { > + compatible = "qcom,sa8775p-gpdsp-anoc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + lpass_ag_noc: interconnect-lpass-ag-noc { > + compatible = "qcom,sa8775p-lpass-ag-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + mc_virt: interconnect-mc-virt { > + compatible = "qcom,sa8775p-mc-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + mmss_noc: interconnect-mmss-noc { > + compatible = "qcom,sa8775p-mmss-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + nspa_noc: interconnect-nspa-noc { > + compatible = "qcom,sa8775p-nspa-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + nspb_noc: interconnect-nspb-noc { > + compatible = "qcom,sa8775p-nspb-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + pcie_anoc: interconnect-pcie-anoc { > + compatible = "qcom,sa8775p-pcie-anoc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + system_noc: interconnect-system-noc { > + compatible = "qcom,sa8775p-system-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + intc: interrupt-controller@17a00000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x20000>; > + reg = <0x17a00000 0x10000>, /* GICD */ > + <0x17a60000 0x100000>; /* GICR * 8 */ > + interrupts = ; compatible reg interrupts interrupt-controller #interrupt-cells redistributor-stride #redistributor-regions #address-cells #size-cells ranges; please > + }; > + > + apps_rsc: rsc@18200000 { > + compatible = "qcom,rpmh-rsc"; > + reg = <0x18200000 0x10000>, > + <0x18210000 0x10000>, > + <0x18220000 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; > + interrupts = , > + , > + ; Wrong indentation > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <2>; > + qcom,tcs-config = , > + , > + , > + ; > + label = "apps_rsc"; Is it used anywhere? > + > + apps_bcm_voter: bcm_voter { > + compatible = "qcom,bcm-voter"; > + }; > + > + rpmhcc: clock-controller { > + compatible = "qcom,sa8775p-rpmh-clk"; > + #clock-cells = <1>; > + clock-names = "xo"; > + clocks = <&xo_board_clk>; clocks clock-names #clock-cells please > + }; > + > + rpmhpd: power-controller { > + compatible = "qcom,sa8775p-rpmhpd"; > + #power-domain-cells = <1>; > + operating-points-v2 = <&rpmhpd_opp_table>; operating-points-v2 #power-domain-cells please > + > + rpmhpd_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + rpmhpd_opp_ret: opp1 { > + opp-level = ; > + }; > + > + rpmhpd_opp_min_svs: opp2 { > + opp-level = ; > + }; > + > + rpmhpd_opp_low_svs: opp3 { > + opp-level = ; > + }; > + > + rpmhpd_opp_svs: opp4 { > + opp-level = ; > + }; > + > + rpmhpd_opp_svs_l1: opp5 { > + opp-level = ; > + }; > + > + rpmhpd_opp_nom: opp6 { > + opp-level = ; > + }; > + > + rpmhpd_opp_nom_l1: opp7 { > + opp-level = ; > + }; > + > + rpmhpd_opp_nom_l2: opp8 { > + opp-level = ; > + }; > + > + rpmhpd_opp_turbo: opp9 { > + opp-level = ; > + }; > + > + rpmhpd_opp_turbo_l1: opp10 { > + opp-level = ; > + }; > + }; > + }; > + }; > + > + arch_timer: timer { Unnecessary label > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; Shouldn't the last one be 10? > + clock-frequency = <19200000>; Please remove this property, the 100 levels of firmware that boot before Linux already program this. > + }; > + > + memtimer: timer@17c20000 { Unnecessary label > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + compatible = "arm,armv7-timer-mem"; > + reg = <0x17c20000 0x1000>; > + clock-frequency = <19200000>; Ditto + please sort to: compatible reg #addr #size ranges > + > + frame@17c21000 { > + frame-number = <0>; > + interrupts = , > + ; > + reg = <0x17c21000 0x1000>, > + <0x17c22000 0x1000>; reg interrupts frame-number [status] please > + }; > + > + frame@17c23000 { > + frame-number = <1>; > + interrupts = ; > + reg = <0x17c23000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17c25000 { > + frame-number = <2>; > + interrupts = ; > + reg = <0x17c25000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17c27000 { > + frame-number = <3>; > + interrupts = ; > + reg = <0x17c27000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17c29000 { > + frame-number = <4>; > + interrupts = ; > + reg = <0x17c29000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17c2b000 { > + frame-number = <5>; > + interrupts = ; > + reg = <0x17c2b000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17c2d000 { > + frame-number = <6>; > + interrupts = ; > + reg = <0x17c2d000 0x1000>; > + status = "disabled"; > + }; > + }; > + > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x1f40000 0x20000>; > + #hwlock-cells = <1>; > + }; > + > + tlmm: pinctrl@f000000 { > + compatible = "qcom,sa8775p-pinctrl"; > + reg = <0xf000000 0x1000000>; All address fields under /soc should be padded to 8 hex digits and nodes should be sorted by their unit address. > + interrupts = ; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 149>; > + }; > + > + qcom-wdt@17c10000 { > + compatible = "qcom,kpss-wdt"; > + reg = <0x17c10000 0x1000>; > + clocks = <&sleep_clk>; > + interrupts = ; Please reorder interrupts and clocks. > + }; > + > + qupv3_id_1: geniqup@ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0xac0000 0x6000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; > + iommus = <&apps_smmu 0x443 0x0>; > + status = "disabled"; > + > + uart10: serial@a8c000 { > + compatible = "qcom,geni-uart"; > + reg = <0xa8c000 0x4000>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, > + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + power-domains = <&rpmhpd SA8775P_CX>; > + operating-points-v2 = <&qup_opp_table_100mhz>; > + status = "disabled"; > + }; > + }; > + > + apps_smmu: apps-smmu@15000000 { > + compatible = "qcom,sa8775p-smmu-500", "arm,mmu-500"; > + reg = <0x15000000 0x100000>, <0x15182000 0x28>; Only one reg is used (unless you're nvidia)... > + reg-names = "base", "tcu-base"; ..and this becomes irrelevant. > + #iommu-cells = <2>; > + qcom,skip-init; > + qcom,use-3-lvl-tables; These two don't exist upstream. > + #global-interrupts = <2>; > + #size-cells = <1>; > + #address-cells = <1>; > + ranges; There are no child nodes of SMMU, please remove. > + > + interrupts = , > + , Bad indentation (or my mail client is drunk again) Konrad > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > + }; > +};